Self-biased Darlington amplifier
View Patent ↗An apparatus comprising a Darlington transistor pair and a bias circuit. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The bias circuit may be coupled between an output transistor of said Darlington transistor pair and the input node. The bias circuit generally comprises (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of the bias transistor and base of the output transistor.
1. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
an isolation resistor coupled between said input node and a collector of said bias transistor, said isolation resistor configured to improve low frequency radio frequency (RF) response.
2. The apparatus according to claim 1 , wherein said bias circuit further comprises:
an emitter bias resistor configured to set a class A, AB, B or other quiescent bias state.
3. The apparatus according to claim 1 , further comprising:
a low noise filter implementation (i) comprising at least one choke inductor and at least one bypass capacitor and (ii) coupled between said bias transistor and said input node.
4. The apparatus according to claim 1 , further comprising:
a feedback resistor coupled between a collector of said bias transistor and said output node, said feedback resistor configured to set the bias current of said apparatus.
5. The apparatus according to claim 1 , wherein said apparatus is monolithically integrated.
6. The apparatus according to claim 1 , wherein said apparatus is packaged in a 3-terminal package.
7. The apparatus according to claim 1 , wherein said apparatus comprises a self-bias Darlington amplifier.
8. The apparatus according to claim 1 , wherein said apparatus is tolerant to supply and temperature variations.
9. The apparatus according to claim 1 , wherein said apparatus enables dynamic bias operation.
10. The apparatus according to claim 1 , wherein said apparatus is implemented using 3.3V SiGe HBT and Si BJT Darlington gain blocks.
11. The apparatus according to claim 1 , wherein said Darlington transistor pair comprises a distributed Darlington amplifier.
12. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
means for coupling between an output transistor of said Darlington transistor pair and said input node comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
means for implementing an isolation resistor coupled between said input node and a collector of said bias transistor, said isolation resistor configured to improve low frequency radio frequency (RF) response.
13. A method for self-biasing a Darlington amplifier comprising the steps of:
(A) implementing a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
(B) coupling a bias circuit between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
(C) coupling an isolation resistor between said input node and a collector of said bias transistor, said isolation resistor configured to improve low frequency radio frequency (RF) response.
14. The method according to claim 13 , wherein said bias circuit further comprises:
an emitter bias resistor configured to set a class A, AB, B or other quiescent bias state.
15. The method according to claim 13 , further comprising:
implementing a low noise filter (i) comprising at least one choke inductor and at least one bypass capacitor and (ii) coupled between said bias transistor and said input node.
16. The method according to claim 13 , further comprising:
implementing a bias feedback resistor coupled between said collector of said bias transistor and said output node.
17. The method according to claim 13 , wherein said Darlington transistor pair and said bias circuit are monolithically integrated.
18. The method according to claim 13 , wherein said Darlington transistor pair and said bias circuit are packaged in a 3-terminal package.
19. The method according to claim 13 , further comprising the step of:
implementing a filter comprising at least one bypass capacitor coupled between said bias transistor and said input node.
20. The method according to claim 13 , further comprising the step of:
implementing a filter comprising at least one inductor coupled between said bias transistor and said input node.
21. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor having a collector coupled to said input node, (b) a bypass capacitor, and (c) a choke resistor connected between a base of said bias transistor and base of said output transistor.
22. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a choke resistor connected between a base of said bias transistor and base of said output transistor; and
a low noise filter implementation coupled between said bias transistor and said input node, comprising at least one choke inductor and at least one bypass capacitor.
23. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
a low noise filter implementation coupled between said bias transistor and said input node, comprising at least one choke inductor.
24. The apparatus according to claim 23 , further comprising:
a feedback resistor coupled between said output node and said input node of said Darlington transistor pair.
25. The apparatus according to claim 23 , further comprising:
a feedback resistor coupled between a collector of said bias transistor and said output node.
26. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
a low noise filter implementation coupled between said bias transistor and said input node, comprising at least one bypass capacitor.
27. The apparatus according to claim 26 , further comprising:
a feedback resistor coupled between said output node and said input node of said Darlington transistor pair.
28. The apparatus according to claim 26 , further comprising:
a feedback resistor coupled between said output node and a collector of said bias transistor.
29. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
a feedback resistor coupled between a collector of each transistor of said Darlington transistor pair and said input node of said Darlington transistor pair.
30. The apparatus according to claim 29 , wherein said feedback resistor is used to set the nominal bias current of said apparatus.
31. The apparatus according to claim 29 , further comprising:
a filter coupled to a collector of said bias transistor.
32. The apparatus according to claim 31 , wherein said filter comprises at least one bypass capacitor.
33. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
a feedback resistor coupled between a collector of the bias transistor and a collector of each transistor of said Darlington transistor pair.
34. The apparatus according to claim 33 , wherein said apparatus further comprises:
an isolation resistor coupled between said input node and a collector of said bias transistor, said isolation resistor configured to improve low frequency radio frequency (RF) response.
35. A method for self-biasing a Darlington amplifier comprising the steps of:
(A) implementing a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
(B) coupling a bias circuit between an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of said bias transistor and base of said output transistor; and
(C) implementing a low noise filter comprising at least one choke inductor and at least one bypass capacitor coupled between said bias transistor and said input node.
36. The method according to claim 35 , further comprising the step of:
implementing a feedback resistor coupled between said output node and said input node of said Darlington pair.