IP Library Granted Patent US 7,388,239
Granted Patent B2
US 7,388,239 · App. 10/623,533 · Granted Jun 17, 2008

Frame shutter pixel with an isolated storage node

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,388,239
App. No.
10/623,533
Granted
Jun 17, 2008
Kind
B2
Abstract

A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.

Claims (21)

1. A method comprising:

receiving a photoelectrically induced signal in an array of photoreceptors on a semiconductor substrate;

controlling each photoreceptor in the array of photoreceptors to simultaneously initiate a common integration period;

at the end of each integration period, controlling each photoreceptor in the array of photoreceptors to transfer its photoelectrically induced signal to a respective storage node located within a respective semiconductor well region formed in the semiconductor substrate; and

preventing each storage node from integrating charge,

wherein each storage node is doped to a first conductivity type, and

wherein a portion of each semiconductor well surrounding each storage node is doped to a second conductivity type.

2. The method of claim 1 , wherein said preventing comprises shielding each storage node with a light shield overlying at least said respective storage node.

3. The method of claim 1 , wherein said preventing comprises shielding each semiconductor well with a light shield overlying said respective semiconductor well.

4. The method of claim 3 , further comprising enabling a first reset operation which resets a value of each storage node, and enabling a second reset operation, which resets a value of each photoreceptor.

5. The method of claim 4 , wherein said first and second reset operations each comprises activating a gate within each semiconductor well.

6. The method of claim 5 , wherein each photoelectrically induced signal is a signal indicative of charge produced by a respective photoreceptor during said integration period.

7. The method of claim 5 , wherein each photoreceptor includes a photodiode.

8. The method of claim 5 , wherein each photoreceptor includes a photogate.

9. The method of claim 3 , further comprising preventing each photoreceptor from acquiring a photoelectrically induced signal which is greater than a pre-determined amount.

10. The method of claim 3 , wherein each of the plurality of photoreceptors in the array comprises a second semiconductor well.

11. The method of claim 10 , further comprising removing charge from each photoreceptor with an anti blooming gate located within each second semiconductor well.

12. The method of claim 10 , further comprising resetting each photoreceptor with reset gates located within each second semiconductor wells.

13. The method of claim 1 , further comprising resetting each storage node with a reset transistor provided within each semiconductor well.

14. The method of claim 1 , further comprising transferring charge from each photoreceptor to each storage node with a transfer gate provided within each semiconductor well region.

15. The method of claim 1 , further comprising isolating each storage node with a bridge diffusion node located within each semiconductor well region.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2016
From: PHOTOBIT CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040188/0115 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2016
From: FOSSUM, ERIC R.; BARNA, SANDOR L.
To: PHOTOBIT CORPORATION
Reel/Frame 040155/0712 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2016
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 040155/0741 →