Microcomputer and microprocessor having flash memory operable from single external power supply
View Patent ↗A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.
1. A microprocessor on a semiconductor substrate comprising:
a central processing unit;
a flash memory array including:
a first region to be stored therein with a program for the central processing unit, and
a second region to be stored therein with information,
wherein the first and the second region each include electrically erasable and programmable non-volatile memory elements each of which has a layer to store electrons;
a volatile memory circuit capable of storing the information therein; and
a peripheral circuit of the flash memory array coupled to the volatile memory circuit,
wherein the information is transferred from the second region to the volatile memory circuit in response to an initializaton operation of the microprocessor, and then the peripheral circuit is controlled by the information stored in the volatile memory circuit.
2. A microprocessor according to claim 1 , wherein the initialization operation includes a reset operation of the semiconductor integrated circuit.
3. A microprocessor according to claim 1 , wherein the electrically erasable and programmable non-volatile memory elements each includes a control gate.
4. A microprocessor according to claim 3 , wherein the electrically erasable and programmable non-volatile memory elements each include a floating gate as the layer to store electrons.
5. A microprocessor according to claim 1 , wherein said information comprises trimming data.