Flat profile structures for bipolar transistors
View Patent ↗A method for fabricating a bipolar transistor includes forming collector, base, and emitter semiconductor layers on a substrate such that the layers form a vertical sequence with respect to an adjacent surface of the substrate. The method includes etching away a portion of a top one of the semiconductor layers to expose a portion of the base semiconductor layer and then, growing semiconductor on the exposed portion of the base layer. The top one of the semiconductor layers is the layer of the sequence that is located farthest from the substrate. The growing causes grown semiconductor to laterally surround a vertical portion of the top one of the semiconductor layers.
1. An integrated circuit, comprising:
a substrate having a top surface;
collector, base, and emitter semiconductor layers of a bipolar transistor, the semiconductor layers forming a vertical sequence on the substrate in which intrinsic portions of two of the semiconductor layers are sandwiched between the top surface of the substrate and a remaining top one of the semiconductor layers, the base layer comprising an extrinsic portion that laterally encircles a vertical portion of the top one of the semiconductor layers; and
a dielectric sidewall being interposed between the vertical portion of the top one of the semiconductor layers and the extrinsic portion of the base layer; and
wherein the substrate includes a subcollector that forms an electrical contact for the collector layer, the entire subcollector being located outside of the portion of the substrate that is vertically below part of the base layer.
2. The integrated circuit of claim 1 , wherein the extrinsic portion of the base layer extends farther away from the substrate than an interface between the top one of the semiconductor layers and the base layer.
3. The integrated circuit of claim 1 , wherein a part of the extrinsic portion of the base layer is located between the substrate and an extrinsic portion of the top one of the semiconductor layers.
4. The integrated circuit of claim 3 , further comprising a dielectric layer, a portion of the dielectric layer being located on the extrinsic portion of the base layer and the extrinsic portion of the top one of the semiconductor layers being located on the dielectric layer.
5. The integrated circuit of claim 3 , wherein the extrinsic portion of the base layer extends farther away from the substrate than an interface between the top one of the semiconductor layers and the base layer.
6. The integrated circuit of claim 5 , further comprising a dielectric layer, a portion of the dielectric layer being located on the part of the extrinsic portion of the base layer and the extrinsic portion of the top one of the semiconductor layers being located on the dielectric layer.
7. The integrated circuit of claim 3 , wherein the dielectric sidewall has a thickness of 500 to 1500 angstroms.
8. The integrated circuit of claim 1 , wherein the top one of the collector, base, and emitter semiconductor layers is epitaxially grown.
9. The integrated circuit of claim 1 , wherein the top one of the collector, base, and emitter semiconductor layers is a graded layer.
10. The integrated circuit of claim 1 , wherein the top one of the collector, base, and emitter semiconductor layers includes gallium.
11. The integrated circuit of claim 1 , wherein the top one of the collector, base, and emitter semiconductor layers includes an InP layer.
12. The integrated circuit of claim 1 , wherein the base layer comprises gallium.
13. The integrated circuit of claim 1 , wherein the base layer comprises gallium, indium and arsenic.
14. The integrated circuit of claim 1 , wherein the substrate is an InP substrate.