Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
1. A semiconductor integrated circuit device that operates while being connected to an external processing unit, comprising:
a plurality of internal memories;
a first processing unit for data processing and a second processing unit for data processing;
a first data bus connected to the first processing unit;
a second data bus connected to the second processing unit;
a third data bus dedicated to the external processing unit;
a first bus selector for selectively connecting the first processing unit with the first data bus or the second data bus;
a second bus selector for selectively connecting the second processing unit with the first data bus or the second data bus;
a first memory interface, mediating and controlling DMA data transfer requests from the first processing unit and second processing unit, which is interposed between the memory assigned to the first processing unit and the first data bus;
a second memory interface, mediating and controlling DMA data transfer requests from the first processing unit and second processing unit, which is interposed between the memory assigned to the second processing unit and the second data bus;
a third memory interface, controlling a data transfer, which is interposed between the memory assigned to the external processing unit and the third data bus; and
a memory configuration controller for controlling the assignment of the plurality of internal memories to the first processing unit, the second processing unit and the external processing unit in accordance with an application.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the memory configuration controller further has the function to control the assignment of external memory to the first processing unit, the second processing unit and the external processing unit, in accordance with an application.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein the memory configuration controller comprises a first register for specifying the assignment of the plurality of internal memories and the external memory; and
wherein data transfer between the first to third data buses is accomplished by rewriting the content of the first register.
4. The semiconductor integrated circuit device according to claim 3 ,
wherein the first register is configured such that it can specify which of the plurality of internal memories and the external memory is unused.
5. The semiconductor integrated circuit device according to claim 2 ,
wherein the memory configuration controller comprises a second register for specifying the respective storage capacities of the plurality of internal memories and the external memory.
6. The semiconductor integrated circuit device according to claim 1 ,
wherein the first processing unit comprises a local memory; and
wherein DMA data transport can be carried out between the local memory and the memory assigned to the first processing unit.
7. The semiconductor integrated circuit device according to claim 1 , further comprising:
a host interface that is interposed between the external processing unit and the third data bus; and
a third bus selector for selectively connecting the host interface with the first data bus or the second data bus.
8. The semiconductor integrated circuit device according to claim 1 , further comprising:
a fourth bus selector for selectively connecting the third data bus with the third memory interface or the second data bus.
9. The semiconductor integrated circuit device according to claim 8 , configured such that a relative address is supplied by the external processing unit when the fourth bus selector selects a connection between the third data bus and the third memory interface, whereas an absolute address is supplied by the external processing unit when the fourth bus selector selects a connection between the third data bus and the second data bus.
10. A portable communication terminal, comprising a semiconductor integrated circuit device according to any of claims 1 , 2 – 5 and 6 – 9 for image processing.