IP Library Granted Patent US 6,897,555
Granted Patent B1
US 6,897,555 · App. 10/626,366 · Granted May 24, 2005

Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,897,555
App. No.
10/626,366
Granted
May 24, 2005
Kind
B1
Abstract

A BGA package having a multiplicity of power segments configured for power connection to integrated circuit die is disclosed. The BGA package substrate includes an integrated circuit die and a ground ring. The substrate also includes a first power ring with a plurality of spaced apart first power ring segments arranged around the die. A second power ring having a plurality of spaced apart conductive second ring segments is also formed around the die. A plurality of vias that penetrate through the substrate are provided to accommodate electrical connections to the segments of the first and second power rings and to the ground ring. The package includes bonding wires for connecting the die to the first and second ring segments and ground ring. Additionally, the package is commonly encapsulated to protect the die and wires. In some implementations, the conductive first ring segments are arranged in staggered configuration relative to the conductive second ring segments with each of the first ring segments having a conductive tab configured so that it passes through spaces between the conductive second ring segments. The tabs electrically connecting the first ring segments to vias.

Claims (57)

1. A BGA package, which comprises:

a substrate having a front side and a back side;

a die attachment region formed on the front side of the substrate;

an electrically conductive first power ring that includes a plurality of spaced apart conductive first ring segments formed on the front side of the substrate, the first ring segments being arranged around the die attachment region;

an electrically conductive second power ring that includes a plurality of spaced apart conductive second ring segments formed on the front side of the substrate, the second ring segments being arranged around the die attachment region and positioned at a greater distance from the die attachment region than the first ring segments;

a plurality of vias penetrating through the substrate, including: a subgroup of first vias which are connected to the first ring segments of the first power ring; and a subgroup of second vias which are connected to the second ring segments of the second power ring;

a semiconductor die mounted over the die attachment region on the front side of the substrate, the semiconductor chip having a plurality of bond pads;

bonding wires for connecting the plurality of bond pads of the die to associated first ring segments and second ring segments;

wherein the each of the first ring segments includes a conductive tab that electrically connects the first ring segments to at least some of the first vias; and

wherein the conductive tabs of the first ring segments are arranged so that they pass through spaces between the plurality of spaced apart conductive second ring segments.

2. The BGA package of claim 1 , further including a third conductive ring arranged around the die attachment region and positioned at a closer distance to the dic attachment region than the first and second power rings.

3. The BGA package of claim 2 , wherein the third conductive ring is a ground ring.

4. The BGA package of claim 3 , wherein the ground ring is formed of a plurality of spaced apart conductive ground ring segments, at least some of the ground ring segments being independently grounded.

5. The BGA package of claim 1 , wherein each of the first ring segments of the first power ring and each of the second ring segments of the second power ring comprise separate power sources.

6. The BGA package of claim 1 , wherein the plurality of spaced apart conductive first ring segments are arranged in staggered configuration relative to the plurality of spaced apart conductive second ring segments.

7. The BGA package of claim 1 , wherein the each of the first ring segments is connected to at least two of the first vias.

8. The BGA package of claim 7 , wherein the each of the first ring segments includes a conductive tab that electrically connects each first ring segment to an associated one of the first vias; and

wherein the conductive tabs of the first ring segments are arranged so that they pass through spaces between the plurality of spaced apart conductive second ring segments.

9. The BGA package of claim 7 , wherein the first ring segments of the first power ring are longer than the second ring segments of the second power ring.

10. A BGA package as in claim 1 further including an encapsulation layer which protectively encases the front side of the substrate encasing at least a portion of the semiconductor die and the bonding wires; and

a plurality of solder balls formed on the back side of the substrate, at least some of the solder balls being electrically connected to the vias.

11. A BGA package as in claim 1 wherein the first power ring includes sixteen (16) spaced apart conductive first ring segments; and

wherein the second power ring includes sixteen (16) spaced apart conductive second ring segments.

12. A BGA package as in claim 1 wherein the first power ring includes twenty four (24) spaced apart conductive first ring segments; and

wherein the second power ring includes twenty (20) spaced apart conductive second ring segments.

13. A BGA package, which comprises:

a substrate having an integrated circuit die mounted on the front side of the substrate;

an electrically conductive first power ring that includes a plurality of spaced apart conductive first ring segments formed on the front side of the substrate around the die;

an electrically conductive second power ring that includes a plurality of spaced apart conductive second ring segments formed on the front side of the substrate, the second ring segments also being arranged around the die;

an electrically conductive ground ring formed on the front side of the substrate around the die;

a plurality of vias penetrating through the substrate including: a subgroup of first vias which are connected to the first ring segments of the first power ring; a subgroup of second vias which are connected to the second ring segments of the second power ring; and a subgroup of ground vias which are connected to the ground ring;

bonding wires for connecting the die to the first ring segments, second ring segments, and ground ring;

wherein the each of the first ring segments includes a conductive tab that electrically connects the first ring segments to at least some of the first vias; and

wherein the conductive tabs of the first ring segments are arranged so that they pass through spaces between the plurality of spaced apart conductive second ring segments.

14. The BGA package of claim 13 , wherein at least some of the first ring segments and the second ring segments provide independent power sources to electronic systems contained within the die.

15. The BGA package of claim 13 , wherein the plurality of spaced apart conductive first ring segments are arranged in staggered configuration relative to the plurality of spaced apart conductive second ring segments.

16. The BGA package of claim 13 , wherein the ground ring is formed of a plurality of spaced apart conductive ground ring segments, at least some of the ground ring segments being independently grounded.

17. The BGA package of claim 13 , wherein at least a portion of the die and bonding wires are contained within an encapsulant.

18. A BGA substrate, which comprises:

a substrate having a die attachment region formed on a front side of the substrate;

an electrically conductive first power ring that includes a plurality of spaced apart conductive first ring segments formed on the front side of the substrate, the first ring segments being arranged around the die attachment region;

an electrically conductive second power ring that includes a plurality of spaced apart conductive second ring segments formed on the front side of the substrate, the second ring segments being arranged around the die attachment region and positioned at a greater distance from the die attachment region than the first ring segments;

a plurality of vias penetrating through the substrate, including:

a subgroup of first vias which are connected to the first ring segments of the first power ring; and

a subgroup of second vias which are connected to the second ring segments of the second power ring;

each of the first ring segments includes a conductive tab that electrically connects the first ring segments to at least some of the first vias; and

the conductive tabs of the first ring segments are arranged so that they pass through spaces between the plurality of spaced apart conductive second ring segments.

19. The BGA package of claim 18 , further including a third conductive ring arranged around the die attachment region and positioned at a closer distance to the die attachment region than the first and second power rings.

20. The BGA package of claim 19 , wherein the third conductive ring is a ground ring.

21. The BGA package of claim 20 , wherein the ground ring is formed of a plurality of spaced apart conductive ground ring segments, at least some of the ground ring segments being independently grounded.

22. The BGA package of claim 18 , wherein each of the first ring segments of the first power ring and each of the second ring segments of the second power ring comprise separate power sources.

23. The BGA package of claim 18 , wherein the each of the first ring segments is connected to at least two of the first vias.

24. A BGA package as in claim 18 , further including a plurality of solder balls formed on the back side of the substrate, at least some of the solder balls being electrically connected to the vias.

25. A BGA package as in claim 18 wherein the first power ring includes sixteen (16) spaced apart conductive first ring segments; and

wherein the second power ring includes sixteen (16) spaced apart conductive second ring segments.

26. A BGA package as in claim 18 wherein the first power ring includes twenty four (24) spaced apart conductive first ring segments; and

wherein the second power ring includes twenty (20) spaced apart conductive second ring segments.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →