Circuit design method to control access pointers of different memory
View Patent ↗A circuit design method to control access pointers of different memory used to transfer the data buffer of printers. The proposed control signal circuit employs a read control signal circuit and a write control signal circuit to receive and send m+n-bit control signals, respectively, to control the access pointers of a memory with 2 m *2 n -register to perform buffer transfer in printers. The disclosed method is able to solve the problem that only one memory block is accessible in sequential mode before. In addition, the method is able to use all memory blocks in buffer transfer in sequential mode to increases the efficiency of data buffering when printing.
1. A circuit design method to control access pointers of different memory, which employs an (m+n)-bit read control signal circuit and an (m+n)-bit write control signal circuit to control the access pointers of a memory with 2 m -block, and each block has 2 n -register in order to perform buffer access of printers, comprising the following steps:
retrieving the previous addresses of the read and write pointers;
receiving a control signal from a data source;
analyzing the control signal to extract a transfer mode, an access mode, and an access number;
determining the control signal circuit (r — ptr or w — ptr) according to the transfer mode and the access mode;
transforming the access number to determine a memory block control circuit (r — ptr — f or w — ptr — f) and a register control circuit (r — ptr — 1 or w — ptr — 1);
setting the access pointers pointing to the corresponding memory addresses of the memory block control circuit and the register control circuit; and
performing a data access of the corresponding memory addresses.
2. In accordance with the method in claim 1 , wherein the data source is a central processing unit.
3. In accordance with the method in claim 1 , wherein the control signal comprises the transfer mode, the access mode and the access number.
4. In accordance with the method in claim 3 , wherein the transfer mode comprises a parallel mode and a sequential mode.
5. In accordance with the method in claim 4 , wherein the method further comprises the steps to determine the print mode control signal circuit set to perform the buffer access in said parallel mode or said sequential mode according to the access mode in the control signals.
6. In accordance with the method in claim 3 , wherein the access number is a decimal number.
7. In accordance with the method in claim 1 , wherein the control signal circuit comprises the read control signal circuit and the write control signal circuit.
8. In accordance with the method in claim 1 , wherein the transformation of the access number is to transform the number into an (m+n)-bit binary number.
9. In accordance with the method in claim 1 , wherein the memory block control circuit is determined by an m-bit binary number.
10. In accordance with the method in claim 1 , wherein the register control signal circuit is determined by an n-bit binary number.