IP Library Granted Patent US 7,116,964
Granted Patent B2
US 7,116,964 · App. 10/628,788 · Granted Oct 3, 2006

Signal reception and processing method for cordless communications systems

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Quick Facts
Patent No.
US 7,116,964
App. No.
10/628,788
Granted
Oct 3, 2006
Kind
B2
Abstract

Channel selection of a received signal is first of all carried out, in the process, by way of an analog channel selection filter. The signal is then converted to a digital discrete-time and discrete-value signal. Finally, the continuous-time and continuous-value signal profile is determined on the basis of a mathematical reconstruction using the zero crossings {t i } and the phase values {φ(t i )=k i ·π/2, k i εN 0 }, with a mathematical reconstruction algorithm using a function system {φ(t−k)}.

Claims (28)

1. A method for processing a signal, which comprises the following steps:

receiving the signal;

carrying out channel selection with an analog channel selection filter;

converting the signal to a digital, discrete-time and discrete-value signal; and

mathematically reconstructing a continuous-time and continuous-value signal profile using zero crossings {t i } and phase values {φ(t i )=k i ·π/2, k i εN 0 } by way of a mathematical reconstruction algorithm using an orthogonal function system {φ(t−k)}.

2. The method according to claim 1 , wherein the receiving step comprises receiving a digitally modulated signal in a cordless communications system.

3. The method according to claim 1 , which comprises limiting the signal and oversampling the limited signal for digitizing the received signal.

4. The method according to claim 3 , wherein the oversampling step comprises producing a signal with a word length of 1.

5. The method according to claim 1 , which comprises FSK-modulating the signal.

6. The method according to claim 1 , which comprises converting a signal frequency to an intermediate frequency after the channel selection.

7. A method for processing a signal, which comprises the following steps:

receiving the signal;

carrying out channel selection with an analog channel selection filter;

converting the signal to a digital, discrete-time and discrete-value signal;

mathematically reconstructing a continuous-time and continuous-value signal profile using zero crossings {t i } and phase values {φ(t i )=k i ·π/2, k i εN 0 } by way of a mathematical reconstruction algorithm using a function system {φ(t−k)}; and

carrying out group delay time equalization in a signal path downstream from the mathematical reconstruction.

8. A receiver circuit for a cordless communications system, comprising:

an analog signal processing section and a digital signal processing section;

said analog signal processing section containing a channel selection filter;

said digital signal processing section containing a phase reconstruction circuit for mathematical reconstruction of a continuous-time and continuous-value signal profile using zero crossings {t i } and periodic phase values {φ(t i )=k i ·π/2, k i εN 0 }, by way of a mathematical reconstruction algorithm using a function system {φ(t−k)}; and

said digital signal processing section having a group delay time equalizer for equalization of at least signal distortion caused by said channel selection filter.

9. The receiver circuit according to claim 8 , wherein said group delay time equalizer is an all-pass filter.

10. A receiver circuit for a cordless communications system, comprising:

an analog signal processing section and a digital signal processing section connected to said analog signal processing section;

said analog signal processing section containing a channel selection filter;

said digital signal processing section containing a phase reconstruction circuit programmed to process a mathematical reconstruction algorithm using a function system {φ(t−k)} for mathematical reconstruction of a continuous-time and continuous-value signal profile using zero crossings {t i } and periodic phase values {φ(t i )=k i ·π/2, k i εN 0 }; and

said digital signal processing section includes a group delay time equalizer for equalization of at least signal distortion caused by said channel selection filter.

11. The receiver circuit according to claim 10 , wherein said group delay time equalizer is an all-pass filter.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2006
From: MEHRGARDT, SOENKE; NEUBAUER, ANDRE
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018009/0780 →