Tri-state detection circuit for use in devices associated with an imaging system
View Patent ↗A tri-state detection circuit includes a first input port for receiving a tri-state input signal, a clock input port for receiving a clocking signal, a first output port, a second output port coupled to the first input port, a D-flip-flop and a buffer. The D-flip-flop has a D input, a clock input CLK, and a Q output. The D input is tied high. The clock input CLK is coupled to the first input port. The Q output is coupled to the first output port. The buffer has a buffer input and a buffer output. The buffer input is coupled to the clock input port. The buffer output is coupled to the clock input CLK of the D-flip-flop.
1. A supply item comprising a circuit including a tri-state input port, said supply item associated with an imaging apparatus, and said supply item having at least three modes of operation, wherein a particular mode of operation of said at least three modes of operation is selected based on a signal level of a tri-state input signal supplied to said tri-state input port.
2. The supply item of claim 1 , wherein said supply item is a printhead cartridge.
3. The supply item of claim 1 , wherein said circuit is formed on a printhead attached to said supply item.
4. A supply item comprising a circuit including a tri-state input port, and said supply item having at least three modes of operation, wherein a particular mode of operation of said at least three modes of operation is selected based on a signal level of a tri-state input signal supplied to said tri-state input port,
wherein said circuit further includes:
a clock input port for receiving a clocking signal;
a first output port;
a second output port coupled to said tri-state input port;
a D-flip-flop, said D-flip-flop having a D input, a clock input CLK, and a Q output, said D input being tied high, said clock input CLK being coupled to said tri-state input port, and said Q output port ;and
a buffer having a buffer input and a buffer output, said buffer input being coupled to said clock input port, and said buffer output being coupled to said clock input CLK of said D-flip-flop.
5. The supply item of claim 4 , further comprising a decoding circuit coupled to said first output port and said second output port, said decoding circuit providing three discrete outputs corresponding, respectively, to a floating level, a logic high level and a logic low level present at said tri-state input port.
6. The supply item of claim 5 , wherein each of said three discrete outputs is respectively coupled to one of at least three selectable mode devices.
7. An imaging apparatus, comprising:
a controller; and
a supply item including a circuit having a tri-state input port coupled to said controller, said supply item having at least three modes of operation, wherein a particular mode of operation of said at least three modes of operation is selected based on a signal level of a tri-state input signal supplied to said tri-state input port by said controller.
8. The imaging apparatus of claim 7 , wherein said supply item is a printhead cartridge.
9. The imaging apparatus of claim 7 , wherein said circuit is formed on a printhead attached to said supply item.
10. An imaging apparatus, comprising:
a controller; and
a supply item including a circuit having a tri-state input port coupled to said controller, said supply item having at least three modes of operation, wherein a particular mode of operation of said at least three modes of operation is selected based on a signal level of a tri-state input signal supplied to said tri-state input port by said controller,
wherein said circuit further includes: circuit comprising:
a clock input port for receiving a clocking signal;
a first output port;
a second output port;
a D-flip-flop, said D-flip-flop having a D input, a clock input CLK, and a Q output, said D input being tied high, said clock input CLK being coupled to said tri-state input port, and said Q output port ;and
a buffer having a buffer input and a buffer output, said buffer input being coupled to said clock input port, and said buffer output being coupled to said clock input CLK of said D-flip-flop.
11. The imaging apparatus of claim 10 , further comprising a decoding circuit coupled to said first output port and said second output port, said decoding circuit providing three discrete outputs corresponding, respectively, to a floating level, a logic high level and a logic low level present at said tri-state input port.
12. The imaging apparatus of claim 11 , wherein each of said three discrete outputs is respectively coupled to one of at least three selectable mode devices.