System and method for compensating for supply voltage induced clock delay mismatches
View Patent ↗Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.
1. A method of compensating for phase differences between a plurality of signals associated with a plurality of signal levels, comprising steps of:
(a) comparing a rising edge of a first signal associated with a first signal level with a rising edge of a second signal associated with a second signal level;
(b) generating a rising edge compensation signal indicative of a phase difference between the rising edge of the first signal and the rising edge of the second signal;
(c) comparing a falling edge of the first signal with a falling edge of the second signal;
(d) generating a falling edge compensation signal indicative of a phase difference between the falling edge of the first signal and the falling edge of the second signal;
(e) delaying the rising edge of the first signal in response to the rising edge compensation signal; and
(f) delaying the falling edge of the first signal in response to the falling edge compensation signal;
wherein delaying steps (e) comprises buffering the first signal with a buffer transistor and adjusting current flow through the buffer transistor, thereby controlling delay of the rising edge of the first signal through the buffer transistor.
2. The method of claim 1 wherein delaying step (f) comprises adjusting current flow through the buffer transistor thereby controlling delay of the falling edge of the first signal through the buffer transistor.
3. The method of claim 2 wherein generating step (b) comprises generating a rising edge compensation signal indicative of whether the rising edge of the first signal leads the rising edge of the second signal.
4. The method of claim 3 wherein generating step (d) comprises generating a falling edge compensation signal indicative of whether the falling edge of the first signal leads the falling edge of the second signal.
5. The method of claim 4 further comprising a step (h) of: (h) filtering the rising edge compensation signal and the falling edge compensation signal with low-pass filters.