Voltage tolerant circuit for protecting an input buffer
View Patent ↗An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is tolerant HIGH. The p-supply being a V DD voltage supplied to a p-channel transistor in the input buffer. In addition, the p-supply is set to a particular voltage when the input voltage to the input buffer is LOW, the particular voltage being at a specific value such that input transistors within the input buffer do not experience overstress voltages. Optionally, p-supply can be prevented from supplying current to the input buffer when an input voltage to the input buffer is tolerant HIGH.
1. A voltage tolerant circuit for protecting an input buffer, comprising:
an n-channel pass gate transistor having a first terminal coupled to a pad I/O, a second terminal coupled to an input of an input buffer, and a gate coupled to an internal ring voltage (Ring V DD );
a p-supply p-channel transistor having a gate coupled to the pad I/O, a first terminal coupled to Ring V DD , and a second terminal coupled to a p-supply of the input buffer, wherein the p-supply is a voltage supplied to a p-channel transistor in the input buffer; and
a p-channel transistor having a first terminal coupled the pad I/O, a gate coupled to Ring V DD , and a second terminal coupled to a first terminal of an n-channel transistor.
2. A voltage tolerant circuit as recited in claim 1 , wherein the n-channel transistor further includes a gate coupled to Ring V DD and a second terminal coupled to the p-supply of the input buffer.
3. A voltage tolerant circuit as recited in claim 1 , wherein the input buffer is an inverter.
4. A voltage tolerant circuit as recited in claim 3 , wherein the inverter includes a p-channel transistor having a first terminal coupled to the p-supply of the input buffer, a gate coupled to the input of the input buffer, and a second terminal coupled to an output of the input buffer.
5. A voltage tolerant circuit as recited in claim 4 , wherein the inverter further includes an n-channel transistor having a first terminal coupled to the output of the input buffer, a gate coupled to the input of the input buffer, and a second terminal coupled to ground.
6. A voltage tolerant circuit as recited in claim 1 , wherein the voltage tolerant I/O is implemented utilizing an I/O generator.
7. A voltage tolerant architecture, comprising:
an input buffer having an input, an output, and a p-supply, wherein the p-supply is a voltage supplied to a p-channel transistor in the input buffer; and
a voltage tolerant I/O circuit having an n-channel pass gate transistor having a first terminal coupled to a pad I/O and a second terminal coupled to an input of an input buffer, and a p-supply p-channel transistor having a gate coupled to the pad I/O a first terminal coupled to Ring V DD , and a second terminal coupled to the p-supply of the input buffer, the voltage tolerant I/O circuit further comprising a p-channel transistor having a first terminal coupled to the pad I/O a gate coupled to Ring V DD , and a second terminal coupled to a first terminal of an n-channel transistor.
8. A voltage tolerant architecture as recited in claim 7 , wherein the n-channel transistor further includes a gate coupled to Ring V DD and a second terminal coupled to the p-supply of the input buffer.
9. A voltage tolerant architecture as recited in claim 7 , wherein the input buffer is an inverter.
10. A voltage tolerant architecture as recited in claim 9 , wherein the inverter includes a p-channel transistor having a first terminal coupled to the p-supply of the input buffer, a gate coupled to the input of the input buffer, and a second terminal coupled to an output of the input buffer.
11. A voltage tolerant architecture as recited in claim 7 , wherein the voltage tolerant I/O circuit is implemented utilizing an I/O generator.