Pseudorandom data pattern verifier with automatic synchronization
View Patent ↗Systems and methods for synchronizing digital communications links, wherein one embodiment implemented in a receiver of a communications link comprises a shift register coupled to a transmission medium to receive synchronization data and a feedback circuit coupled to the shift register, wherein one or more cells of the shift register are configured to alternatively accept as input either a bit from a preceding cell or a received bit of synchronization data. The first occurs prior to synchronization, while the second occurs after synchronization. A counter is used to assert a signal indicating that the transmitter and receiver are synchronized.
1. A method comprising:
receiving one or more bits of synchronization data in a receiver of a communications link, wherein the synchronization data corresponds to at least one bit from a corresponding transmitter shift register;
loading the one or more bits of synchronization data into a shift register in the receiver, wherein the receiver shift register has a feedback circuit;
if the receiver shift register is filled with synchronization data, initiating synchronized operation of the receiver shift register with a corresponding transmitter shift register, wherein during synchronized operation, a bit sequence generated by the receiver shift register is compared to a received bit sequence to identify the occurrence of errors in a data transmission from the transmitter; and
if the receiver shift register is not filled with synchronization data, shifting the loaded synchronization data and loading one or more additional bits of synchronization data into the receiver shift register.
2. The method of claim 1 , wherein receiving one or more bits of synchronization data comprises receiving idle codes containing synchronization data.
3. The method of claim 1 , further comprising determining whether the receiver shift register is filled with synchronization data by counting a predetermined number of cycles after a reset event.
4. The method of claim 1 , wherein the receiver shift register comprises a plurality of serially coupled flip-flops, and wherein shifting the loaded synchronization data comprises shifting the bit in each flip-flop to a next flip-flop.
5. The method of claim 1 , wherein loading the one or more additional bits of synchronization data into the receiver shift register comprises loading the one or more additional bits of synchronization data into one or more predetermined cells of the receiver shift register.