IP Library Granted Patent US 7,170,238
Granted Patent B2
US 7,170,238 · App. 10/631,387 · Granted Jan 30, 2007

Control systems and methods

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,170,238
App. No.
10/631,387
Granted
Jan 30, 2007
Kind
B2
Abstract

Control systems and methods. An embodiment of control system may comprise a processor for receiving control signals from at least one input device when linked thereto. Computer-readable program code is provided for generating output signals at the processor based on the control signals. An interface is operatively associated with the processor, the interface configures at least one regulator based on the output signals generated at the processor by delivering pulse width modulated signals to the at least one regulator.

Claims (48)

1. A method for controlling at least one regulator, comprising:

receiving control signals at a processor;

generating output signals at the processor based on the control signals;

configuring the at least one regulator based on the output signals; and

maintaining the output of the at least one regulator in the event of a power source failure.

2. The method of claim 1 , further comprising addressing the output signals to the at least one regulator.

3. The method of claim 1 , further comprising shutting off a load operatively associated with the at least one regulator.

4. The method of claim 1 , wherein configuring the at least one regulator is based on analog signals.

5. The method of claim 1 , wherein configuring the at least one regulator is based on digital signals.

6. The method of claim 1 , further comprising providing at least one auxiliary power source for configuring the at least one regulator.

7. A control system, comprising:

a processor for receiving control signals from at least one input device when linked thereto;

computer-readable program code for generating output signals at said processor based on the control signals; and

an interface operatively associated with said processor, said interface configuring at least one regulator based on the output signals generated at said processor by delivering pulse width modulated signals to the at least one regulator.

8. The control system of claim 7 , wherein said processor is linked to said at least one input device via a CAN bus.

9. The control system of claim 7 , wherein said computer-readable program code comprises at least one script.

10. The control system of claim 7 , wherein said output signals generated at said processor comprise at least a data component and an address component.

11. The control system of claim 7 , wherein said output signals generated at said processor comprise a shutoff signal.

12. The control system of claim 7 , wherein the regulator controls at least one gas discharge lamp.

13. The control system of claim 7 , wherein said interface converts the output signals generated by said processor to analog voltage signals.

14. The control system of claim 7 , wherein said interface converts the output signals generated by said processor to current signals.

15. The control system of claim 7 , further comprising program code for converting said interface between voltage-control and current-control modes.

16. The control system of claim 7 , wherein said interface configures the at least one regulator by delivering digital signals to the at least one regulator.

17. The control system of claim 7 , further comprising at least one auxiliary power source for providing electrical power to said interface.

18. The control system of claim 7 , further comprising an external watchdog timer operatively associated with said processor, said watchdog timer indicating the operational status of said processor.

19. The control system of claim 7 , further comprising a dual-mode reset circuit operatively associated with said processor, said reset circuit for resetting said processor.

20. The control system of claim 7 , wherein said interface supports a plurality of different types of regulators.

21. The control system of claim 7 , wherein said interface further comprises:

a digital to analog converter;

an operational amplifier operatively associated with said digital to analog converter, said operational amplifier increasing control granularity of the at least one regulator.

22. The control system of claim 21 , wherein said interface further comprises a field effect transistor operatively associated with said operational amplifier, said field effect transistor changing the functionality of said operational amplifier to a comparator when the processor issues an OFF signal.

23. The control system of claim 21 , wherein said interface further comprises a light-emitting diode operatively associated with said field effect transistor, said light-emitting diode indicating the operational status of said interface.

24. A control system, comprising:

a processor for receiving control signals from at least one input device when linked thereto;

computer-readable program code for generating output signals at said processor based on the control signals; and

an interface operatively associated with said processor, said interface configuring at least one regulator based an the output signals generated at said processor, wherein said interface comprises a digital to analog converter and an operational amplifier operatively associated with said digital to analog converter, said operational amplifier increasing control granularity of the at least one regulator.

25. The control system of claim 24 , wherein said interface further comprises a field effect transistor operatively associated with said operational amplifier, said field effect transistor changing the functionality of said operational amplifier to a comparator when the processor issues an OFF signal.

26. The control system of claim 24 , wherein said interface further comprises a light-emitting diode operatively associated with said field effect transistor, said light-emitting diode indicating the operational status of said interface.

27. A control system, comprising:

a processor for receiving control signals from at least one input device when linked thereto;

computer-readable program code for generating output signals at said processor based on the control signals;

an interface operatively associated with said processor, said interface configuring at least one regulator based on the output signals generated at said processor; and

program code for converting said interface between voltage-control and current-control modes.

28. A control system, comprising:

a processor for receiving control signals from at least one input device when linked thereto;

computer-readable program code for generating output signals at said processor based on the control signals;

an interface operatively associated with said processor, said interface configuring at least one regulator based on the output signals generated at said processor; and

a dual-mode reset circuit operatively associated with said processor, said reset circuit for resetting said processor.

Assignments (6)
CHANGE OF NAME Recorded Dec 5, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044695/0115 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2013
From: AUTOMATED CONTROL TECHNOLOGY PARTNERS, INC.
To: GOOGLE INC.
Reel/Frame 031515/0743 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2013
From: 3VNET,INC.
To: AUTOMATED CONTROL TECHNOLOGY PARTNERS, INC.
Reel/Frame 030460/0468 →
CHANGE OF NAME Recorded Mar 28, 2013
From: COLORADO VNET CORP
To: 3VNET, INC.
Reel/Frame 030111/0296 →
CHANGE OF NAME Recorded Sep 3, 2010
From: RUSSOUND ACQUISITION CORP.
To: COLORADO VNET CORP.
Reel/Frame 024933/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2010
From: COLORADO VNET, LLC
To: RUSSOUND ACQUISITION CORP.
Reel/Frame 024823/0476 →