IP Library › Granted Patent US 6,992,532
Granted Patent B2
US 6,992,532 · App. 10/631,833 · Granted Jan 31, 2006

IGFET and tuning circuit

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Quick Facts
Patent No.
US 6,992,532
App. No.
10/631,833
Granted
Jan 31, 2006
Kind
B2
Abstract

A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

Claims (49)

1. A tuning circuit comprising:

a first reactance;

a second reactance; and

an insulated gate field effect transistor having a gate arranged to receive a control signal, the first reactance being connected between the source of the field effect transistor and a first node and the second reactance having the same value as the first reactance and being connected between the drain of the field effect transistor and a second node; and

wherein the first and second nodes are arranged so as to experience a balanced ac signal and there being no circuit connection for grounding the source and drain of said transistor.

2. A circuit according to claim 1 , wherein the first and second reactances are capacitors.

3. A circuit according to claim 1 , wherein the first and second reactances are inductors.

4. A circuit according to claim 1 , including a capacitor connected between said nodes.

5. A circuit according to claim 1 , including an inductor connected between said nodes.

6. A tuning circuit comprising:

a first reactance;

a second reactance; and

an insulated gate field effect transistor having a gate arranged to receive a control signal;

the first reactance being connected between the source of the field effect transistor and a first node and the second reactance having the same value as the first reactance and being connected between the drain of the field effect transistor and a second node;

wherein

the first and second nodes are arranged so as to experience a balanced ac signal; and

the insulated gate field effect transistor comprises source and drain regions within a surrounding region and gate electrode means provided over a channel or channels between said source and drain regions and over at least part of the boundary between said source and drain regions and said surrounding region, said surrounding region being provided with ground connection means for connection to an AC ground.

7. A tuning circuit according to claim 6 , wherein said ground connection means comprises a plurality of interconnected ohmic contacts to said surrounding region.

8. A tuning circuit according to claim 6 , wherein said gate electrode means encompasses said source and drain regions.

9. A tuning circuit according to claim 6 , wherein said source and drain regions are in a finger structure arrangement.

10. A tuning circuit according to claim 6 , wherein said source and drain regions are in a waffle structure arrangement.

11. A tuning circuit according to claim 6 , including a plurality of source and drain regions and an interconnection layer in which said source regions are connected together and said drain regions are connected together, the conductor or conductors of the interconnection layer being connected to said source and drain regions by splaying conductive paths.

12. A tuning circuit according to claim 11 , wherein said source and drain regions are in a waffle structure arrangement.

13. A tuning circuit according to claim 12 , wherein the interconnection layer comprises a source interconnection structure and a drain interconnection structure, said structures comprising respective sets of fingers extending diagonally, with respect to said waffle structure arrangement, which are interdigitated.

14. A tuning circuit according to claim 6 , wherein the first and second reactances are capacitors.

15. A tuning circuit according to claim 6 , wherein the first and second reactances are inductors.

16. A tuning circuit according to claim 6 , including a capacitor connected between said nodes.

17. A tuning circuit according to claim 6 , including an inductor connected between said nodes.

18. A resonant circuit including a tuning circuit, the tuning circuit comprising:

a first reactance;

a second reactance; and

an insulated gate field effect transistor having a gate arranged to receive a control signal;

the first reactance being connected between the source of the field effect transistor and a first node and the second reactance having the same value as the first reactance and being connected between the drain of the field effect transistor and a second node;

wherein

the first and second nodes are arranged so as to experience a balanced ac signal; and

the insulated gate field effect transistor comprises source and drain regions within a surrounding region and gate electrode means provided over a channel or channels between said source and drain regions and over at least part of the boundary between said source and drain regions and said surrounding region, said surrounding region being provided with ground connection means for connection to an AC ground.

19. A resonant circuit according to claim 18 , wherein said ground connection means comprises a plurality of interconnected ohmic contacts to said surrounding region.

20. A resonant circuit according to claim 18 , wherein said gate electrode means encompasses said source and drain regions.

21. A resonant circuit according to claim 18 , wherein said source and drain regions are in a finger structure arrangement.

22. A resonant circuit according to claim 18 , wherein said source and drain regions are in a waffle structure arrangement.

23. A resonant circuit according to claim 18 , including a plurality of source and drain regions and an interconnection layer in which said source regions are connected together and said drain regions are connected together, the conductor or conductors of the interconnection layer being connected to said source and drain regions by splaying conductive paths.

24. A resonant circuit according to claim 23 , wherein said source and drain regions are in a waffle structure arrangement.

25. A resonant circuit according to claim 24 , wherein the interconnection layer comprises a source interconnection structure and a drain interconnection structure, said structures comprising respective sets of fingers extending diagonally, with respect to said waffle structure arrangement, which are interdigitated.

26. A resonant circuit according to claim 18 , wherein the first and second reactances are capacitors.

27. A resonant circuit according to claim 18 , wherein the first and second reactances are inductors.

28. A resonant circuit according to claim 18 , including a capacitor connected between said nodes.

29. A resonant circuit according to claim 18 , including an inductor connected between said nodes.

30. A resonant circuit according to claim 18 , comprising an oscillator.

31. A resonant circuit according to claim 18 , comprising a filter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2012
From: NOKIA CORPORATION
To: RPX CORPORATION
Reel/Frame 028323/0196 →