Nonvolatile memory cell with multiple floating gates formed after the select gate
View Patent ↗In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 ) formed after the select gate. Substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions protrude above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric ( 164 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates ( 160 ). A dielectric layer ( 164 ) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate ( 140 ). Each control gate ( 160 ) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions ( 220 ) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.
1. A method for fabricating a nonvolatile memory, the method comprising:
(1) forming a first conductive gate for a nonvolatile memory cell;
(2) after the operation (1), forming conductive floating gates FG 1 and FG 2 for the memory cell.
2. The method of claim 1 wherein the operation (2) further comprises forming conductive gates CG 1 and CG 2 for the memory cell, wherein the gates CG 1 , CG 2 are insulated from each other and from the first conductive gate.
3. The method of claim 2 wherein the gate CG 1 overlies the gate FG 1 , and the gate CG 2 overlies the gate FG 2 .
4. The method of claim 1 wherein the first conductive gate and the gates FG 1 and FG 2 overlie a semiconductor substrate and are insulated from the substrate;
wherein the memory cell comprises two source/drain regions in the substrate and a channel region extending between the two source/drain regions under the gates FG 1 and FG 2 and the first conductive gate.
5. The method of claim 1 wherein a width of the first conductive gate is smaller than the minimum photolithographic line width.
6. The method of claim 1 wherein a width of the first conductive gate is smaller than the width of any one of gates FG 1 , FG 2 .
7. The method of claim 1 wherein forming the first conductive gate comprises:
forming a conductive layer; and
etching the conductive layer;
wherein the etching operation comprises horizontal etching to reduce the width of the first conductive gate.
8. The method of claim 1 wherein forming the first conductive gate comprises:
forming a conductive layer;
etching the conductive layer to form a conductive feature having sidewalls;
reacting the material of the sidewalls with another material to form a reaction product on the sidewalls; and
removing the reaction product.
9. The method of claim 8 wherein the reacting operation comprises oxidation of the material of the conductive layer to form an oxide on the sidewalls.
10. The method of claim 8 further comprising, after removing the reaction product on the sidewalls, oxidizing the sidewalls to form a dielectric on the sidewalls to insulate the first conductive gate from the gates FG 1 and FG 2 .