Universal interface
View Patent ↗A universal interface apparatus having a processor for receiving one or more Network Interface signals having a transport mechanism associated therewith. The transport mechanism may include Asynchronous Transfer Mode, Internet Protocol, Frame Relay, Integrated Services Digital Network, High bit-rate Digital Subscriber Line, Asymmetric Digital Subscriber Line, Very High Data Rate Digital Subscriber Line, Symmetric Digital Subscriber Line, 10 base T, 100 Base T, Gigabit Ethernet and E1/T1. The processor may recognize the transport mechanism associated with each Network Interface signal. In the event Asynchronous Transfer Mode is recognized as the transport mechanism, the processor may also segment perform Asynchronous Transfer Mode (ATM) adaptation layer processing on each Network Interface signal. Further, the universal interface apparatus includes a bus interface device for generating a System Interface signal from the Asynchronous Transfer Mode (ATM) adaptation layer processed Network Interface signal in response to the recognized transport mechanism.
1. An interface apparatus comprising:
a processor for receiving at least one network interface signal, and for recognizing a transport mechanism associated with each network interface signal;
a bus interface device for generating at least one system interface signal in response to the recognized transport mechanism; wherein:
the transport mechanism comprises at least one of Asynchronous Transfer Mode, Internet Protocol, Frame Relay, Integrated Services Digital Network, High bit-rate Digital Subscriber Line, Asymmetric Digital Subscriber Line, Very High Data Rate Digital Subscriber Line, Symmetric Digital Subscriber Line, 10 base T, 100 base T, Gigabit Ethernet and E1/T1;
the processor further examines a pattern for each network interface signal to recognize the associated transport mechanism;
each system interface signal is coupled with at least one of a circuit switched interface, a packet switched interface, and a combined circuit packet switched interface;
the transport mechanism comprises an adaptation layer of Asynchronous Transfer Mode, the processor performs ATM adaptation layer processing on each Network Interface signal in response to the recognized transport mechanism; and
at least one of the processor and the bus interface device matches a timing of the circuit switched interface and formats the ATM adaptation layer processed network interface signal to the corresponding system interface signal.
2. The interface apparatus of claim 1 , comprising a control switch for partitioning and switching the performance of the matching the timing and the performance of the formatting the ATM adaptation layer processed network interface signal between the processor and the bus interface device in response to a control signal.
3. An interface apparatus comprising:
a processor for receiving at least one network interface signal, and for recognizing a transport mechanism associated with each network interface signal;
a bus interface device for generating at least one system interface signal in response to the recognized transport mechanism; wherein:
the transport mechanism comprises at least one of Asynchronous Transfer Mode, Internet Protocol, Frame Relay, Integrated Services Digital Network, High bit-rate Digital Subscriber Line, Asymmetric Digital Subscriber Line, Very High Data Rate Digital Subscriber Line, Symmetric Digital Subscriber Line, 10 base T, 100 base T, Gigabit Ethernet and E1/T1;
the processor further examines a pattern for each Network Interface signal to recognize the associated transport mechanism;
each system interface signal is coupled with at least one of a circuit switched interface, a packet switched interface, and a combined circuit packet switched interface;
at least one of the processor and the bus interface device converts each network interface signal to correspond with the packet switched interface and routes each converted network interface signal; and
the interface apparatus further comprises a control switch for partitioning and switching the performance of each said network interface signal conversion and each said network interface signal routing in response to a control signal between the processor and the bus interface device.