IP Library Granted Patent US 8,903,348
Granted Patent B2
US 8,903,348 · App. 10/632,051 · Granted Dec 2, 2014

Serial radio frequency to baseband interface with power control

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Quick Facts
Patent No.
US 8,903,348
App. No.
10/632,051
Granted
Dec 2, 2014
Kind
B2
Abstract

An interface between an RF processing section and a baseband processing section supports general purpose message transmission as well as satellite positioning system signal sample transmission between the RF processing section and the baseband processing section. The interface includes a bi-directional message interface and a data interface. The message interface supports transmission of power control messages to the RF processing section to provide detailed control over activation or de-activation of individual blocks of hardware circuitry in the RF processing section.

Claims (13)

1. An RF front end for a satellite positioning system receiver, the front end comprising:

an RF processing section comprising an RF input for receiving satellite positioning system signals;

an RF to baseband interface coupled to the RF processing section, the interface comprising:

a bi-directional message interface for communicating messages between the RF processing section and a baseband processing section, including receiving a power control message from the baseband processing section wherein the power control message is associated with power consumption of the RF processing section, wherein the RF section includes a register for receiving the power control message from the baseband section and wherein devices to be controlled by the power control message are coupled to the register to receive respective power control data from the received power control message;

a data interface for communicating data from the RF processing section to the baseband processing section;

wherein the message interface comprises:

a message clock line;

a message-in signal line and

a message-out signal line; and

wherein the message-out signal line carries an output bit stream representing the power control message, the data interface comprises a data clock signal line and a data bit signal line; and

the data clock signal line carries a data clock comprising a rising edge and a falling edge;

the data bit signal line carries a data signal comprising a sign bit and a magnitude bit; and

the first data bit is valid on the rising edge of the data clock and the second data bit is valid on the falling edge of the data clock.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: CSR TECHNOLOGY INC.
To: QUALCOMM INCORPORATED
Reel/Frame 069221/0001 →
CHANGE OF NAME Recorded Dec 22, 2011
From: SIRF TECHNOLOGY, INC.
To: CSR TECHNOLOGY INC.
Reel/Frame 027437/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2003
From: GRONEMEYER, STEVEN; TSO, ROBERT
To: SIRF TECHNOLOGY INC.
Reel/Frame 014818/0651 →