Instruction prefetch caching for remote memory
View Patent ↗A disk drive control system comprising a micro-controller, a micro-controller cache system adapted to store micro-controller data for access by the micro-controller, a buffer manager adapted to provide the micro-controller cache system with micro-controller requested data stored in a remote memory, and a cache demand circuit adapted to: a) receive a memory address and a memory access signal, and b) cause the micro-controller cache system to fetch data from the remote memory via the buffer manager based on the received memory address and memory access signal prior to a micro-controller request.
1. A cache control system connectable to a remote memory, the cache control system comprising:
a micro-controller for executing micro-controller data;
a buffer manager for arbitrating access to the remote memory;
a micro-controller cache system including a cache memory, the micro-controller cache system coupled to the micro-controller and the buffer manager for fetching and caching micro-controller data stored in the remote memory via the buffer manager for access by the micro-controller; and
a cache demand circuit coupled to the micro-controller and the micro-controller cache system for receiving an address in the remote memory from the micro-controller and transmitting the address to the micro-controller cache system;
wherein the micro-controller cache system is responsive to the transmitted address to fetch micro-controller executable data stored at that particular transmitted address into the cache memory before the micro-controller requests that the micro-controller executable data be forwarded to the micro-controller, and
wherein, after the micro-controller cache system has fetched the micro-controller executable data, the micro-controller requests execution of the micro-controller executable data.
2. The cache control system of claim 1 , wherein the cache demand circuit is further responsive to a memory access signal to transmit the address to the micro-controller cache system.
3. The cache control system of claim 2 , wherein the cache demand circuit receives the memory access signal from the micro-controller.
4. The cache control system of claim 3 , wherein the memory access signal comprises a write signal received from the micro-controller.
5. The cache control system of claim 2 , further comprising an interrupt circuit for interrupting the micro-controller based on a transmitted interrupt signal.
6. The cache control system of claim 5 , wherein the memory access signal comprises the transmitted Interrupt signal.
7. The cache control system of claim 6 , wherein the micro-controller executable data fetched by the micro-controller cache system is executed by the micro-controller during a micro-controller interrupt service routine.
8. The cache control system of claim 2 , wherein the cache demand circuit receives the address from the micro-controller before the memory access signal.
9. The cache control system of claim 2 , wherein the cache demand circuit is operable to store the address received from the micro-controller.
10. The cache control system of claim 2 , wherein the cache demand circuit is operable to transmit the memory access signal to the micro-controller cache system.
11. The cache control system of claim 2 , wherein the memory access signal comprises a servo-interrupt signal.
12. The cache control system of claim 2 , wherein the memory access signal comprises a host-interrupt signal.
13. The cache control system of claim 1 , wherein the buffer manager is in communication with a plurality of disk drive control system clients, including at least one of a disk subsystem, an error correction code subsystem, and a host interface subsystem.
14. A method for caching micro-controller data in a cache control system comprising a micro-controller, a buffer manager coupled to a remote memory, a micro-controller cache system having a cache memory and coupled to the micro-controller and the buffer manager, and a cache demand circuit coupled to the micro-controller and the micro-controller cache system, the method comprising:
receiving at the cache demand circuit an address in the remote memory from the micro-controller;
transmitting the address from the cache demand circuit to the microcontroller cache system;
fetching microcontroller executable data stored at the address via the buffer manager;
caching the micro-controller executable data stored at that particular transmitted address in the cache memory before the micro-controller requests that the microcontroller executable data be forwarded to the micro-controller; and
after the micro-controller executable data has been cached, requesting execution of the micro-controller executable data at the micro-controller.
15. The method of claim 14 , further comprising receiving at the cache demand circuit a memory access signal, and wherein the step of transmitting the address from the cache demand circuit to the micro-controller cache system is taken upon receipt of the memory access signal.
16. The method of claim 15 , further comprising transmitting the memory access signal from the micro-controller to the cache demand circuit.
17. The method of claim 15 , wherein the memory access signal comprises a write signal.
18. The method of claim 15 , wherein the memory access signal comprises an interrupt signal.
19. The method of claim 18 , further comprising executing the micro-controller executable data stored at the address during a microcontroller interrupt service routine.
20. The method of claim 15 , wherein the step of receiving the address occurs before the step of receiving the memory access signal.
21. The method of claim 15 , further comprising storing the address in the cache demand circuit.
22. The method of claim 15 , further comprising transmitting the memory access signal from the cache demand circuit to the micro-controller cache system.
23. The method of claim 15 , wherein the memory access signal comprises a servo-interrupt signal.
24. The method of claim 15 , wherein the memory access signal comprises a host-interrupt signal.