IP Library Granted Patent US 7,249,224
Granted Patent B2
US 7,249,224 · App. 10/635,703 · Granted Jul 24, 2007

Methods and apparatus for providing early responses from a remote data cache

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Quick Facts
Patent No.
US 7,249,224
App. No.
10/635,703
Granted
Jul 24, 2007
Kind
B2
Abstract

According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. If information for responding to a request is available in a remote data cache, a response with a completion indicator is provided to the requesting processor. The completion indicator allows the request to be met without having to probe local or remote nodes.

Claims (29)

1. A method for providing a response to a cache access request, the method comprising:

receiving a cache access request associated with a memory line at a cache coherence controller from a processor in a cluster of processors, the cluster of processors interconnected in a point-to-point architecture;

obtaining response information for the cache access request from a remote data cache associated with the cache coherence controller, wherein the remote data cache receives data and state information for memory lines of remote clusters, each remote cluster including a plurality of remote cluster processors;

determining that the cache access request can be handled locally by using the remote data cache without having to probe remote nodes; and

providing response information with a completion indicator to the processor when it is determined that the cache access request can be handled locally.

2. The method of claim 1 , wherein the cache access request can be handled locally if a valid copy of the memory line is in the remote data cache.

3. The method of claim 1 , wherein response information includes state information.

4. The method of claim 2 , wherein the completion indicator is a completion bit.

5. The method of claim 1 , wherein the completion indicator notifies the processor that the response information from the cache coherence controller will be the only response information.

6. The method of claim 1 , wherein the processor is a request processor in a request cluster.

7. The method of claim 1 , wherein the completion indicator allows the cache coherence controller to avoid probing local or remote nodes.

8. The method of claim 1 , wherein the processor sends a source done upon identifying the completion indicator in the response information.

9. The method of claim 8 , wherein the processor sends the source done to the cache coherence controller.

10. The method of claim 9 , wherein the processor sends the source done to the cache coherence controller acting as a memory controller.

11. A processing cluster, comprising:

a plurality of processors interconnected in a point-to-point architecture;

a cache coherence controller configured to receive a cache access request associated with a memory line from a first processor amongst the plurality of processors, obtain response information for the cache access request from a remote data cache associated with the cache coherence controller and provide response information with a completion indicator to the processor if it is determined that a valid copy of the memory line is in the remote data cache, wherein the remote data cache receives data and state information for memory lines of remote clusters, each remote cluster including a plurality of remote cluster processors.

12. The processing cluster of claim 11 , wherein response information is provided in a response packet.

13. The processing cluster of claim 11 , wherein response information includes stale information.

14. The processing duster of claim 12 , wherein response information includes data.

15. The processing cluster of claim 11 , wherein the completion indicator notifies the first processor that the response information from the cache coherence controller will be the only response information.

16. The processing cluster of claim 11 , wherein the first processor is a request processor in a request cluster.

17. The processing cluster of claim 11 , wherein the completion indicator allows the cache coherence controller to avoid probing local or remote nodes.

18. The processing cluster of claim 11 , wherein the first processor sends a source done upon identifying the completion indicator in the response information.

19. The processing cluster of claim 18 , wherein the first processor sends the source done to the cache coherence controller.

20. A cache coherence controller, comprising:

means for receiving a cache access request associated with a memory line at a cache coherence controller from a processor in a cluster of processors, the cluster of processors interconnected in a point-to-point architecture;

means for obtaining response information for the cache access request from a remote data cache associated with the cache coherence controller, wherein the remote data cache receives data and state information for memory lines of remote clusters, each remote cluster including a plurality of remote cluster processors; and

means for providing response information with a completion indicator to the processor after determining tat the cache access request can be completed locally.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2019
From: U.S. BANK NATIONAL ASSOCIATION, SOLELY AS NOTES COLLATERAL AGENT
To: SANMINA CORPORATION; HADCO CORPORATION; HADCO SANTA CLARA; SCI TECHNOLOGY; SENSORWISE, INC.
Reel/Frame 049378/0927 →
SECURITY INTEREST Recorded Aug 3, 2018
From: SANMINA CORPORATION
To: U.S. BANK NATIONAL ASSOCIATION, NOT IN ITS INDIVIDUAL CAPACITY BUT SOLELY AS NOTES COLLATERAL AGENT
Reel/Frame 046797/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2018
From: MEMORY INTEGRITY, LLC
To: SANMINA CORPORATION
Reel/Frame 046249/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2013
From: SANMINA CORPORATION
To: MEMORY INTEGRITY, LLC
Reel/Frame 030585/0980 →
MERGER Recorded Nov 28, 2012
From: SANMINA-SCI CORPORATION
To: SANMINA CORPORATION
Reel/Frame 029368/0472 →
MERGER Recorded Jul 27, 2012
From: NEWISYS, INC.
To: SANMINA-SCI CORPORATION
Reel/Frame 028652/0891 →
RELEASE OF SECURITY INTEREST Recorded Nov 25, 2008
From: CITIBANK, N.A.
To: HADCO SANTA CLARA, INC.; HADCO CORPORATION; SCIMEX, INC.; SANMINA-SCI SYSTEMS HOLDINGS, INC.; SCI TECHNOLOGY, INC.; SANMINA-SCI CORPORATION
Reel/Frame 021890/0312 →
PLEDGE AND SECURITY AGREEMENT Recorded Jan 3, 2005
From: SANMINA-SCI CORPORATION; HADCO CORPORATION; HADCO SANTA CLARA, INC.; SCI TECHNOLOGY, INC.; VIKING INTERWORKS INC.; COMPATIBLE MEMORY, INC.; SCI SYSTEMS, INC.; SANMINA-SCI SYSTEMS (ALABAMA) INC.; SANMINA-SCI SYSTEMS HOLDINGS, INC.; INTERAGENCY, INC.; SANMINA-SCI SYSTEMS ENCLOSURES (DENTON) INC.; SCIMEX, INC.; NEWISYS, INC.; SANMINA-SCI ENCLOSURES USA INC.; SCI PLANT NO. 5, L.L.C.; SCI PLANT NO. 22, L.L.C.; SANMINA GENERAL, L.L.C.; SANMINA LIMITED, L.L.C.; SANMINA-SCI, LLC; SANMINA TEXAS, L.P.
To: CITIBANK, N.A.
Reel/Frame 016097/0729 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2003
From: GLASCO, DAVID B.
To: NEWISYS, INC.
Reel/Frame 014378/0700 →