Static memory cell having independent data holding voltage
View Patent ↗A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.
1. A semiconductor circuit comprising:
a plurality of static memory cells each comprising two load MOS transistors, two driver MOS transistors, and two transfer MOS transistors;
a plurality of word lines coupled to said plurality of static memory cells;
a plurality of data lines coupled to said plurality of static memory cells; and
a peripheral circuit comprising MOS transistors and controlling said plurality of static memory cells,
wherein gate insulators of said two load MOS transistors are thicker than gate insulators of said MOS transistors of said peripheral circuit.
2. The semiconductor circuit according to claim 1 ,
wherein gate insulators of said two driver MOS transistors are thicker than said gate insulators of said MOS transistors of said peripheral circuit.
3. The semiconductor circuit according to claim 2 ,
wherein gate insulators of said transfer MOS transistors are thicker than said gate insulators of said MOS transistors of said peripheral circuit.
4. The semiconductor circuit according to claim 2 ,
wherein a first voltage and a second voltage, which is lower than said first voltage, are supplied to each of said static memory cells, and
wherein said plurality of word lines which are not selected are set to a voltage lower than said second voltage.
5. The semiconductor circuit according to claim 2 ,
wherein a threshold voltage of said transfer MOS transistors is smaller than a threshold voltage of said driver MOS transistors.
6. The semiconductor circuit according to claim 2 ,
wherein a supply voltage of said static memory cells coupled to one of said plurality of word lines during a first period is larger than a supply voltage of said peripheral circuit.
7. The semiconductor circuit according to claim 6 ,
wherein during said first period said one of said plurality of word lines is not selected.
8. The semiconductor circuit according to claim 7 ,
wherein word lines of said plurality of word lines, which are not selected are set to a negative voltage.
9. The semiconductor circuit according to claim 2 ,
wherein said semiconductor circuit is formed on an N type substrate having a P type well, and
wherein said two load MOS transistors of said static memory cell are embedded in said P type well.