Method and system for cascading analyzer trace memories
View Patent ↗Cascaded analyzer trace memories are described herein. According to one embodiment, the method comprises receiving a packet stream in a master analyzer and a slave analyzer, wherein the master analyzer includes a first trace memory, and wherein the slave includes a second trace memory. According to one embodiment, the method further comprises determining whether the first trace memory has been filled past a memory address. According to one embodiment, if the first trace memory has not been filled past the memory address, storing one or more packets of the packet stream in the first trace memory. In one embodiment, if the first trace memory has been filled past the memory address, performing the following operations: marking a location in the first trace memory, transmitting a signal to the slave analyzer, and storing one or more packets of the packet stream in the second trace memory.
1. A method comprising:
receiving a packet stream in a master analyzer and a slave analyzer, wherein
the master analyzer includes a first trace memory, and wherein the slave includes a second trace memory;
determining whether the first trace memory has been filled past a memory address;
if the first trace memory has not been filled past the memory address, storing one or more packets of the packet stream in the first trace memory;
if the first trace memory has been filled past the memory address, performing the following,
marking a location in the first trace memory;
transmitting a signal to the slave analyzer; and
storing one or more packets of the packet stream in the second trace memory.
2. The method of claim 1 , wherein the trace memories include a trigger point.
3. The method of claim 1 wherein, if the first trace memory has been filled past the memory address, storing one or more packets of the packet stream in the first trace memory simultaneously with the storing one or more packets of the packet stream in the second trace memory.
4. The method of claim 1 , wherein, the master analyzer and the slave analyzer operate based on an independent clock.
5. The method of claim 1 , wherein the marking a location in the first trace memory indicates a SEAM.
6. A method comprising:
receiving a set of one or more frames in a first analyzer, wherein the first analyzer includes a first trace memory;
receiving the set in a second analyzer, wherein the second analyzer includes a second trace memory, and wherein the second analyzer and the first analyzer are daisy-chained together;
determining whether the first trace memory has been filled past a memory address; and
after determining the first trace memory has been filled past a memory address, simultaneously storing frames of the set in the first trace memory and the second trace memory.
7. The method of claim 6 further comprising: after determining the first trace memory has been filled past a memory address, marking a SEAM in the first trace memory.
8. The method of claim 6 , wherein the trace memory includes a trigger point.
9. The method of claim 6 , wherein the first analyzer and second analyzer use independent clocks.
10. An apparatus comprising:
a master analyzer including,
a communication link configured to monitor a packet stream; and
a trace memory communicatively coupled to the communication link, wherein the trace memory is to store packets of the packet stream until the trace memory has been filled past a memory address, wherein after the trace memory has been filled past a memory address, the master analyzer is to transmit a signal to a slave analyzer, wherein the signal is to trigger the slave analyzer to store packets of the packet stream in a trace memory of the slave analyzer.
11. The apparatus of claim 10 , wherein the slave analyzer and the master analyzer are to store packets simultaneously until the trace memory is full.
12. The apparatus of claim 10 , wherein the master analyzer and the slave analyzer use a common clock.
13. The apparatus of claim 10 , wherein the master analyzer and the slave analyzer use separate clocks.
14. The apparatus of claim 10 , wherein the trace memory includes a trigger point.
15. The apparatus of claim 10 , wherein after the trace memory has been filled past a memory address, the master analyzer is to store a marker at a memory location in the trace memory.
16. A system comprising:
a host computer, the host computer to receive network communications;
a plurality of analyzers communicatively coupled to the host computer, wherein each of the plurality of analyzers includes a plurality of trace memories that form a single virtual memory space, and wherein ones of the plurality of analyzers are to store certain portions of the network communications in the trace memories; and
a disk array communicatively coupled to one of the plurality of analyzers, wherein the disk array is to store selected contents of the trace memories.
17. The system of claim 16 , wherein each of the plurality of trace memories includes a trigger point.
18. The system of claim 16 , wherein the plurality of analyzers use a common clock.