Analog state recovery technique for DLL design
View Patent ↗A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is arranged to carry a clock signal. The delay locked loop operatively connects to the clock path where the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop. An analog state storage apparatus operatively connects to the delay locked loop and is arranged to store the voltage potential. Also, the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal.
1. An integrated circuit, comprising:
a clock path arranged to carry a clock signal;
a power supply path arranged to receive power from a power supply;
a delay locked loop operatively connected to the power supply path and the clock path, wherein the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop; and
an analog state storage apparatus operatively connected to the delay locked loop, wherein the analog state storage apparatus is arranged to store the voltage potential, and wherein the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal.
2. The integrated circuit of claim 1 , wherein the analog state storage apparatus is arranged to receive a signal indicative of the loss of at least one of the clock signal and the delayed clock signal.
3. An integrated circuit, comprising:
a clock path arranged to carry a clock signal;
a power supply path arranged to receive power from a power supply;
a delay locked loop operatively connected to the power supply path and the clock path, wherein the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop; and
an analog state storage apparatus operatively connected to the delay locked loop, wherein the analog state storage apparatus is arranged to store the voltage potential, and wherein the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal,
wherein the analog state storage apparatus comprises a pass transistor circuit and a capacitor.
4. The integrated circuit of claim 3 , wherein the capacitor is arranged to store the stored voltage potential.
5. The integrated circuit of claim 3 , wherein the pass transistor circuit comprises a switch arranged to control current flow between the voltage potential and an output of the pass transistor circuit.
6. The integrated circuit of claim 3 , wherein the analog state storage apparatus further comprises a unity gain amplifier.
7. An integrated circuit, comprising:
a clock path arranged to carry a clock signal;
a power supply path arranged to receive power from a power supply;
a delay locked loop operatively connected to the power supply path and the clock path, wherein the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop; and
an analog state storage apparatus operatively connected to the delay locked loop, wherein the analog state storage apparatus is arranged to store the voltage potential, and wherein the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal,
wherein the delay locked loop comprises a charge pump operatively connected to a filter capacitor, and wherein the stored voltage potential is dependent on the charge pump and the filter capacitor.
8. The integrated circuit of claim 7 , wherein an output of the charge pump is operatively disabled dependent on a signal indicative of the loss of at least one of the clock signal and the delayed clock signal.
9. The integrated circuit of claim 7 , wherein the analog state storage apparatus is arranged to operatively drive the filter capacitor to recover from the loss of at least one of the clock signal and the delayed clock signal.
10. The integrated circuit of claim 1 , wherein the analog state storage apparatus is arranged to selectively not receive the voltage potential for a fixed time duration.
11. A method for controlling a delay locked loop, comprising:
generating a delayed clock signal;
comparing the delayed clock signal to an input clock signal;
generating a voltage potential dependent on the comparing;
storing the voltage potential; and
operatively using the stored voltage potential to generate the delayed clock signal in response to a loss of at least one of the input clock signal and the delayed clock signal.
12. The method of claim 11 , further comprising:
selectively disconnecting the generated voltage potential from the stored voltage potential in response to the loss of at least one of the input clock signal and the delayed clock signal.
13. The method of claim 12 , wherein the selectively disconnecting comprises selectively propagating the generated voltage potential to the stored voltage potential.
14. The method of claim 11 , further comprising:
buffering the stored voltage potential.
15. A method for controlling a delay locked loop, comprising:
generating a delayed clock signal;
comparing the delayed clock signal to an input clock signal;
generating a voltage potential dependent on the comparing;
storing the voltage potential; and
operatively using the stored voltage potential to generate the delayed clock signal in response to a loss of at least one of the input clock signal and the delayed clock signal,
buffering the stored voltage potential,
wherein the buffering uses a unity gain amplifier.
16. A method for controlling a delay locked loop, comprising:
generating a delayed clock signal;
comparing the delayed clock signal to an input clock signal;
generating a voltage potential dependent on the comparing;
storing the voltage potential; and
operatively using the stored voltage potential to generate the delayed clock signal in response to a loss of at least one of the input clock signal and the delayed clock signal,
wherein the storing uses a capacitor.
17. The method of claim 11 , further comprising:
selectively disabling the generating the voltage potential in response to the loss of at least one of the input clock signal and the delayed clock signal.
18. The method of claim 11 , further comprising:
selectively disconnecting the generated voltage potential from the stored voltage potential for a fixed time duration.
19. An integrated circuit, comprising:
means for generating a delayed clock signal;
means for comparing the delayed clock signal to an input clock signal;
means for generating a voltage potential dependent on the means for comparing;
means for storing the voltage potential; and
means for selectively disconnecting the generated voltage potential from the stored voltage potential in response to a loss of at least one of the input clock signal and the delayed clock signal.
20. The integrated circuit of claim 19 , further comprising:
means for buffering the stored voltage potential.
21. The integrated circuit of claim 19 , further comprising:
means for selectively disabling the generating the voltage potential in response to at least one selected from the loss of at least one of the input clock signal and the delayed clock signal, and a fixed time duration.
22. The integrated circuit of claim 19 , further comprising:
means for indicating the loss of at least one of the clock signal and the delayed clock signal.