Fabrication method for semiconductor integrated circuit device
View Patent ↗To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15 G having an SiGe layer 15 b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF 3 gas. Thereby, the gate electrode 15 G can be formed without causing side etching at two side faces (SiGe layer 15 b ) of the gate electrode 15 G.
1. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming a gate insulating film over a semiconductor wafer;
(b) depositing conductive films having an SiGe layer over the gate insulating film;
(c) forming at least one electrode having the SiGe layer by patterning the conductive films; and
(d) after the step (c), subjecting the semiconductor wafer to a plasma processing in an atmosphere of a mixed gas of (A) a first gas including Ar, He, Ne, Kr, Xe or N 2 , and (B) a second gas including CHF 3 , CF 4 , C 2 F 6 or SF 6 .
2. A method of fabricating a semiconductor integrated circuit device according to claim 1 wherein the second gas is CHF 3 .
3. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein a concentration of Ge of the SiGe layer is equal to or larger than 10% of a total thereof.
4. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein a concentration of Ge of the SiGe layer is equal to or larger than 20% of a total thereof.
5. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein a concentration of Ge of the SiGe layer is equal to or larger than 40% of a total thereof.
6. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein a side etching amount at two side faces of the at least one gate electrode, after the step (d), is equal to or smaller than 40% of a length, in a channel length direction, at a portion of the gate electrode forming film left after the step (c) other than the SiGe layer.
7. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein a width of the SiGe layer of the at least one gate electrode is substantially equal to that of other layers of the at least one gate electrode, after the step (d).
8. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein at least two gate electrodes are formed in the step (c), and wherein a field effect transistor of an n-channel type and a field effect transistor of a p-channel type having the gate electrodes are formed at the semiconductor wafer.
9. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the semiconductor wafer after the step (c) is transferred to the step (d) in a state of maintaining a vacuum state.
10. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the step (b) includes a step of introducing boron to the gate electrode forming film.
11. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the step (b) includes a step of depositing a silicon layer over the SiGe layer, and, after the step (d), the method further comprises the steps of:
(e) forming side wall insulating films at side faces of the at least one gate electrode;
(f) exposing an upper face of the at least one gate electrode and portions of a main face of the semiconductor wafer;
(g) depositing a metal film having a high melting point over the semiconductor wafer; and
(h) forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor wafer.
12. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming a gate insulating film over a main face of a semiconductor wafer;
(b) depositing conductive films over the gate insulating film;
(c) forming a gate electrode by patterning the conductive films; and
(d) after the step (c), subjecting the semiconductor wafer to a plasma processing in an atmosphere of a mixed gas of (A) a first gas including Ar, He, Ne, Kr, Xe or N 2 , and (B) a second gas including CHF 3 , CF 4 , C 2 F 6 or SF 6 ,
wherein the step (b) comprises the substeps of:
(i) depositing an SiGe layer of the conductive films; and
(ii) depositing a silicon layer of the conductive films over the SiGe layer.
13. A method of fabricating a semiconductor integrated circuit device according to claim 12 , wherein the second gas is CHF 3 .
14. A method of fabricating a semiconductor integrated circuit device according to claim 12 , wherein a concentration of Ge of the SiGe layer is equal to or larger than 10% of a total thereof.
15. A method of fabricating a semiconductor integrated circuit device according to claim 12 , wherein a side etching amount at two side faces of the gate electrode, after the step (d), is equal to or smaller than 40% of a length in a channel length direction of the silicon layer left after the step (c).
16. A method of fabricating a semiconductor integrated circuit device according to claim 12 , wherein after the step (d), further comprising the steps of:
(e) forming side wall insulating films at side faces of the gate electrode;
(f) exposing an upper face of the gate electrode and portions of a main face of the semiconductor wafer;
(g) depositing a metal film having a high melting point over the semiconductor wafer; and
(h) forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor wafer.
17. A method of fabricating a semiconductor integrated circuit device according to claim 12 , further comprising the steps of:
after the step (d), introducing a first impurity to an area for forming a field effect transistor of an n-channel type in the semiconductor wafer; and
after the step (d), introducing a second impurity, for forming a semiconductor area of a conductivity type opposite to a conductivity type of a semiconductor area formed by a first impurity, to an area for forming a field effect transistor of a p-channel type in the semiconductor wafer.
18. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming a gate insulating film over a main face of the semiconductor wafer;
(b) depositing conductive films over the gate insulating film;
(c) forming a gate electrode by patterning the conductive films; and
(d) after the step (c), subjecting the semiconductor wafer to a plasma processing in an atmosphere of a mixed gas of (A) a first gas including Ar, He, Ne, Kr, Xe or N 2 , and (B) a second gas including CHF 3 , CF 4 , C 2 F 6 or SF 6 , and
wherein the step (b) comprises the substeps of:
(i) depositing an SiGe layer of the conductive films; and
(ii) depositing a metal layer of the conductive films over the SiGe layer.
19. A method of fabricating a semiconductor integrated circuit device according to claim 18 , wherein a side etching amount at two side faces of the gate electrode after the step (d) is equal to or smaller than 40% of a length in a channel length direction of the metal layer after the step (c).
20. A method of fabricating a semiconductor integrated circuit device according to claim 18 , wherein the step (b) includes a step of depositing the metal layer after introducing boron to the SiGe layer.
21. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein during the plasma processing any side etching of the SiGe layer is such that after the step (d), a side etching amount of the SiGe layer is equal to or less than 40% of a length, in a channel length direction, at a portion of the gate electrode forming film left after the step (c) other than the SiGe layer.
22. A method of fabricating a semiconductor integrated circuit device according to claim 21 , wherein said side etching amount is equal to or less than 20% of said length.
23. A method of fabricating a semiconductor integrated circuit device according to claim 22 , wherein said side etching amount is equal to or less than 10% of said length.
24. A method of fabricating a semiconductor integrated circuit device according to claim 12 wherein during the plasma processing any side etching of the SiGe layer is such that after the step (d), a side etching amount of the SiGe layer is equal to or less than 40% of a length, in a channel length direction, at a portion of the gate electrode forming film left after the step (c) other than the SiGe layer.
25. A method of fabricating a semiconductor integrated circuit device according to claim 24 , wherein said side etching amount is equal to or less than 20% of said length.
26. A method of fabricating a semiconductor integrated circuit device according to claim 25 , wherein said side etching amount is equal to or less than 10% of said length.
27. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the first gas includes Ar, Ne, Kr or N 2 .
28. A method of fabricating a semiconductor integrated circuit device according to claim 12 , wherein the first gas includes Ar, Ne, Kr or N 2 .
29. A method of fabricating a semiconductor integrated circuit device according to claim 18 , wherein the first gas includes Ar, Ne, Kr or N 2 .