Systems and methods for scan test access using bond pad test access circuits
View Patent ↗The present invention is directed to circuits and methods to efficiently conduct scan testing of integrated circuits in which first level packaging is varied to provide different versions of the integrated circuit. An integrated circuit is provided that includes at least one bond pad test circuit. The bond pad test circuit is coupled between a bond pad and functional components within an integrated circuit. In one embodiment, the bond pad test circuit includes a multiplexer and a D flip-flop in which the D input of the flip-flop is coupled to a bond pad. In another embodiment, the bond pad test circuit includes a multiplexer and a D flip-flop in which the D input of the flip-flop is coupled to the output of the multiplexer. A method for scan testing using an integrated circuit with a bond pad test circuit is also provided.
1. An integrated circuit having bond pads and a bond pad test circuit, wherein said bond pad test circuit comprises:
a flip-flop with an input coupled to a bond pad;
a multiplexer with a first input coupled to the bond pad and a second input coupled to an output of said flip-flop,
wherein an output of said multiplexer is coupled to a scan input of another device within said integrated circuit,
wherein said multiplexer further comprises a scan test mode input for controlling whether said multiplexer is in scan test mode; and
wherein said bond pad test circuit enables scan testing of devices within said integrated circuit that are coupled to bond pads that are not electrically coupled external to a package that encapsulates said integrated circuit.
2. The integrated circuit of claim 1 , wherein said bond pad test circuit enables scan testing of devices within said integrated circuit that are coupled to bond pads that remain in an open condition.
3. The integrated circuit of claim 1 , wherein a contact point is coupled to said multiplexer that is external to said package that enables the multiplexer to be toggled between scan test mode and normal operation.
4. The integrated circuit of claim 1 , wherein said bond pad test circuit enables scan testing of devices within said integrated circuit that are coupled to bond pads that are coupled to a fixed voltage or ground.
5. A method for scan testing an integrated circuit that includes at least one bond pad test circuit, comprising the steps of:
(a) toggling a multiplexer coupled to a scan input of a device within the integrated circuit to enable running general scan test patterns;
(b) masking bond pads corresponding to said at least one bond pad test circuit;
(c) running general scan test patterns;
(d) toggling the multiplexer coupled to the scan input of the device within the integrated circuit to enable running bond pad test patterns;
(e) unmasking said bond pads corresponding to said at least one bond pad test circuit; and
(f) running bond pad test patterns for at least one of said bond pads corresponding to a bond pad test circuit.
6. The method of claim 5 , wherein said masking of bond pads comprises applying a scan test mode signal to said at least one bond pad test circuit.
7. The method of claim 5 , wherein said unmasking of bond pads comprises applying a normal operation signal to said at least one bond pad test circuit.