Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer
View Patent ↗A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
1. A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer, comprising:
depositing, by MOCVD, a seed layer of highly crystalline PCMO thin film, having a thickness of between about 50 Å to 300 Å,
depositing a second polycrystalline PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO thin film layer;
increasing the resistance of die combined PCMO thin film layer in a semiconductor device by applying a negative electric pulse; and
decreasing the resistance of the combined PCMO thin film layer in a semiconductor device by applying a positive electric pulse.
2. The method of claim 1 wherein said increasing the resistance of the combined PCMO thin film layer in a semiconductor device by applying a negative electric pulse includes applying an electric pulse of between about −4V to 5V, having a pulse width of between about 75 nsec to 1 μsec.
3. The method of claim 1 where said decreasing the resistance of the combined PCMO thin film layer in a semiconductor device by applying a positive electric pulse includes applying an electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
4. The method of claim 1 which includes post-annealing at high temperature of the combined PCMO thin film layer to enhance the switching and stability properties of the highly crystallized layer, including annealing at a temperature of between about 500° C. to 650° C., for between about 10 minutes to 120 minutes.
5. A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer, comprising:
depositing a seed layer of PCMO thin film by MOCVD;
depositing a second polycrystalline PCMO thin film layer on the seed layer by spin coating wherein the thickness of a combined PCMO thin film layer is between about 500 Å to 3000 Å;
writing to the combined PCMO thin film layer in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 sec to 1 μsec; and
resetting the combined PCMO thin film layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
6. The method of claim 5 wherein said depositing a seed layer of PCMO includes depositing a seed layer of PCMO by MOCVD in highly crystalline form having a thickness of between about 50 Å to 300 Å.
7. The method of claim 5 wherein said depositing a second PCMO thin film layer on the seed layer includes depositing a second PCMO thin film by spin coating having a thickness of between about 500 Å to 3000 Å.
8. The method of claim 5 which includes post-annealing at high temperature of the combined PCMO thin film layer to enhance the switching and stability properties of the highly crystallized layer, including annealing at a temperature of between about 500° C. to 650° C., for between about 10 minutes to 120 minutes in an ambient atmosphere.
9. A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer, comprising:
depositing, by MOCVD, a seed layer of highly crystalline PCMO having a thickness of between about 50 Å to 300 Å,
depositing a second polycrystalline PCMO thin film layer on the seed layer, by spin coating, having a thickness ten times that of the highly crystalline seed layer to form a combined PCMO thin film layer;
increasing the resistance of the combined PCMO thin film layer in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and
decreasing the resistance of the combined PCMCO thin film layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
10. The method of claim 9 which includes post-annealing at high temperature of the combined PCMO thin film layer to enhance the switching and stability properties of the highly crystallized layer, including annealing at a temperature of between shout 500° C. to 650° C., for between about 10 minutes to 120 minutes.