Bidirectional horizontal scan circuit with sub-sampling and horizontal adding functions
View Patent ↗A horizontal scan circuit comprises a column selector and a plurality of block selectors. A column selector is used to address particular columns of pixels within blocks. A block selector is used to select a particular block and to select the particular columns of the selected block that are addressed by the column selector. Each block selector typically comprises a single D-type flip-flop that is associated with a block of pixel columns. The block selectors are arranged such that the blocks can be scanned from left-to-right or right-to-left. The column selector comprises an asynchronous counter and a decoder that are further arranged to provide sub-sampling and horizontal adding functions. The use of block and column selectors reduces the number of relatively large D-type flip-flops (which conserves die area) and reduces the parasitic capacitance associated with the otherwise required relatively large number of inputs of the column selection circuit drivers.
1. A horizontal scan circuit for a pixel array, comprising:
pixel columns within the pixel array that are arranged in blocks such that at least two pixel columns are associated with each block;
a column selector that is configured to receive a column scan clock, a direction mode signal, a subsample signal, and a horizontal adding signal and generate a column address signal for addressing the at least two pixel columns within each of the blocks; and
a scan chain of block selectors that is configured to sequentially select blocks in a first scan direction in response to a block scan clock, and during the period in which a particular block is selected, to select particular pixel columns of the particular selected block, wherein each block selector of the scan chain is associated with an individual block.
2. The circuit of claim 1 , wherein the pixel columns are arranged in blocks such that each block has the same number of associated pixel columns.
3. The circuit of claim 2 , wherein the column selector comprises an asynchronous counter and a decoder having a modulus that is equal to the number of the associated pixel columns in each block.
4. The circuit of claim 3 , wherein the column selector is further configured to operate in a sub-sampling mode wherein not all of the pixel columns within a block are selected in response to the column scan clock, the direction mode signal, and the subsample signal.
5. The circuit of claim 3 , wherein the column selector is further configured to operate in a horizontal adding mode wherein the pixel columns are simultaneously selected in response to the direction mode signal and the horizontal adding signal.
6. The circuit of claim 1 , wherein the column scan clock has a frequency that is at least two times greater than the column scan clock.
7. The circuit of claim 1 , wherein the scan chain of block selectors is further configured to sequentially select blocks in a first and a second scan direction in response to a direction mode signal.
8. A method for horizontally scanning a pixel array, comprising:
arranging in blocks a plurality of pixel columns within the pixel array such that at least two pixel columns are associated with each block;
receiving a column scan clock signal, a direction mode signal, a subsample signal, and a horizontal adding signal and generating in response a column address signal for addressing the at least two pixel columns within each of the blocks;
sequentially selecting blocks in a first scan direction in response to a block scan clock; and
selecting particular pixel columns of the particular selected block during the period in which a particular block is selected.
9. The method of claim 8 , wherein the pixel columns are arranged in blocks such that each block has the same number of associated pixel columns.
10. The method of claim 9 , wherein the column scan clock has a frequency that is at least two times greater than the blockscan clock.
11. The method of claim 10 , wherein the column address signal is generated having a modulus that is equal to the number of the associated pixel columns in each block.
12. The method of claim 8 , wherein not all of the pixel columns within a block are selected in response to the column scan clock, the direction mode signal, and the subsample signal.
13. The method of claim 8 , wherein a plurality of pixel columns are simultaneously selected in response to the direction mode signal and the horizontal adding signal.
14. A circuit for horizontally scanning a pixel array, comprising:
pixel columns within the pixel array that are arranged in blocks such that at least two pixel columns are associated with each block;
means for generating a column address signal for addressing the at least two pixel columns within each of the blocks;
means for sequentially selecting blocks in a first scan direction in response to a block scan clock and a direction mode signal; and
means for selecting particular pixel columns of the particular selected block during the period in which a particular block is selected.
15. The circuit of claim 14 , wherein the pixel columns are arranged in blocks such that each block has the same number of associated pixel columns.
16. The circuit of claim 15 , wherein the column scan clock has a frequency that is at least two times greater than the block scan clock.
17. The circuit of claim 16 , wherein the column address signal is generated having a modulus that is equal to the number of the associated pixel columns in each block.
18. The circuit of claim 14 , wherein not all of the pixel columns within a block are selected in response to the column scan clock, the direction mode signal, and the subsample signal.
19. The circuit of claim 14 , wherein a plurality of pixel columns are simultaneously selected in response to the direction mode signal and the horizontal adding signal.
20. The circuit of claim 14 , further comprising means for sequentially selecting blocks in a first and a second scan direction in response to a direction mode signal.