IP Library Granted Patent US 6,927,141
Granted Patent B2
US 6,927,141 · App. 10/642,837 · Granted Aug 9, 2005

Process for forming fast recovery diode with a single large area P/N junction

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Quick Facts
Patent No.
US 6,927,141
App. No.
10/642,837
Granted
Aug 9, 2005
Kind
B2
Abstract

A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

Claims (6)

1. A reduced mask process for forming a fast recovery diode comprising the steps of forming a field oxide body atop a surface of a semiconductor die; applying a first mask to said field oxide body and etching a large area window therein exposing a portion of said surface of said die and leaving an outer oxide termination ring around said exposed portion; defining a large area P/N junction in said die below said exposed portion; applying a second mask to clear said exposed portion for the application of an anode contact; evaporating platinum metal on an opposing surface of said die and heating said die to drive platinum atoms into said die; depositing metal atop said exposed portion and over the oxide termination ring; and applying a third mask to etch said metal to define an anode contact which overlies said exposed portion and the inner periphery of said termination ring and a separate EQR ring which overlies the outer periphery of said termination ring.

2. The process of claim 1 , wherein said platinum metal has a thickness of about 10 Å and is driven at about 950° C. for about 30 minutes.

3. The process of claim 1 , which includes the further step of depositing an amorphous silicon layer atop said anode contact and said EQR ring, and a further mask step for removing said amorphous silicon from said anode contact overlying said exposed portion, and leaving said amorphous silicon over said EQR ring and the portion of said anode contact overlying said inner periphery of said oxide termination ring.

4. The process of claim 2 , which includes the further step of depositing an amorphous silicon layer atop said anode contact and said EQR ring, and a further mask step for clearing said amorphous silicon from said anode contact overlying said exposed portion, and leaving said amorphous silicon over said EQR ring and the portion of said anode contact overlying said inner periphery of said oxide termination ring.

5. The process of claim 4 , which includes a further mask step for defining a plurality of spaced floating guard ring diffusions under said outer oxide termination ring.

6. A reduced mask process for forming a fast recovery diode comprising the steps of forming a field oxide body atop a surface of a semiconductor die; applying a first mask to said field oxide body and etching a large area window therein exposing a portion of said surface of said die and leaving an outer oxide termination ring around said exposed portion; defining a large area P/N junction in said die below said exposed portion; applying a second mask to clear said exposed portion for the application of an anode contact; evaporating platinum metal on an opposing surface of said die and heating said die to drive platinum atoms into said die; depositing metal atop said exposed portion and over the oxide termination ring; and applying a third mask to etch said metal to define an anode contact which overlies said exposed portion and the inner periphery of said termination ring and a separate EQR ring which overlies the outer periphery of said termination ring; and depositing an amorphous silicon layer atop said anode contact and said EQR ring, and a further mask step for removing said amorphous silicon from said anode contact overlying said exposed portion, and leaving said amorphous silicon over said EQR ring and the portion of said anode contact overlying said inner periphery of said oxide termination ring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2007
From: INTERNATIONAL RECTIFIER CORPORATION
To: SILICONIX TECHNOLOGY C. V.
Reel/Frame 019658/0714 →