Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
View Patent ↗A method of reading data from a plurality of multi-level memory cells. The cells are arranged to correspond to a physical address space, each cell having at least one transistor. Each cell stores 2 n levels of data. A logical address is converted into a physical address included in the physical address space. A determination is made whether a logical address space including the logical address matches the physical address space. The most significant bit (X1) is specified by comparing an output voltage of the transistor corresponding to the most significant bit with a reference voltage when a logical address space matches the physical address space. The specified bit is output from one of the cells corresponding to the physical address. A computer readable medium stores program code for carrying out the method of reading out the plurality of multi-level memory cells.
1. A method of reading n (n≧2) number of bits (X 1 , X 2 , . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2 n levels of data each expressed by the bits (X 1 , X 2 , . . . , and Xn), comprising the steps of:
converting a logical address into a physical address included in the physical address space;
judging whether a logical address space including the logical address matches the physical address space;
specifying the most significant bit X 1 by comparing an output voltage of the transistor corresponding to the most significant bit with a reference voltage when the logical address space matches the physical address space; and
outputting the specified bit from one of the cells corresponding to the physical address.
2. The method according to claim 1 further comprises the step of specifying the bits (X 1 , X 2 , . . . , Xn) by comparing output voltages of the transistor corresponding to the bits (X 1 , X 2 , . . . , Xn) with reference voltages corresponding to the bits (X 2 , . . . , Xn).
3. A computer readable medium storing program code for causing a computer to read n (n≧2) number of bits (X 1 , X 2 , . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2 n levels of data each expressed by the bits (X 1 , X 2 , . . . , Xn), comprising:
first program code means for converting a logical address into a physical address included in the physical address space;
second program code means for judging whether a logical address space including the logical address matches the physical address space;
third program code means for specifying the most significant bit X 1 by comparing an output voltage of the transistor corresponding to the most significant bit with a reference voltage when the logical address space matches the physical address space; and
fourth program code means for outputting the specified bit from one of the cells corresponding to the physical address.
4. The computer readable medium according to claim 3 further comprising the program code means for specifying the bits (X 1 , X 2 , . . . , Xn) by comparing voltages corresponding to the bits (X 1 , X 2 , . . . , Xn) with reference voltages corresponding to the bits (X 1 , X 2 , . . . , Xn) when judged that the logical address space does not match the physical address space.