IP Library Granted Patent US 7,263,139
Granted Patent B1
US 7,263,139 · App. 10/646,101 · Granted Aug 28, 2007

Phase correction for a phase modulated signal with mutually interfering symbols

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Quick Facts
Patent No.
US 7,263,139
App. No.
10/646,101
Granted
Aug 28, 2007
Kind
B1
Abstract

A circuit and method for correcting phase of a received phase modulated (PM) signal. The method uses k most recently received data bits, which alternate between in-phase I and quadrature Q bits, as an address for a lookup table 60 . The lookup table outputs a phase figure 62 derived from a reconstructed waveform. When the most recent k bit is a Q bit, the complement 68 of the phase figure 62 is calculated to yield a phase correction. Otherwise, the phase figure is the phase correction, which is applied to adjust the phase of a delayed version of the received signal. The delayed, phase adjusted signal is then applied to correct the phase of a received signal. The circuit splits an input PM signal in parallel between a matched filter 54 and a delay block 76, 88 . The matched filter output provides the input to a register 58 for storing the k data bits. The delay block holds the PM signal until it is input into a loop phase shifter 78 synchronously with the phase correction. The output of the loop phase filter is input, after filtering, to a primary phase shifter 52 that adjusts phase of a received PM signal.

Claims (44)

1. A method to correct a phase of a received phase modulated (PM) signal, comprising:

applying a received phase modulated (PM) signal to a first circuit branch and a second circuit branch;

in the first circuit branch, selecting k data bits from the received PM signal, wherein a data bit received most recently corresponds to time t 1 and wherein k is an integer greater than 1;

determining a phase error based on the k data bits;

in the second circuit branch, delaying the received PM signal to a second time t 2 that is later than t 1 ;

applying the phase error to at least a portion of the delayed PM signal at the second time t 2 ;

calculating a phase offset based on the delayed PM signal; and

using the phase offset to correct the phase of a PM signal received at a time later than t 1 .

2. The method of claim 1 wherein selecting k data bits comprises arranging the k data bits serially so as to alternate between in-phase and quadrature bits.

3. The method of claim 1 further comprising:

setting k equal to a total number of data bits that influence the phase of the received PM signal at the first time t 1 .

4. The method of claim 1 wherein

k

=

1

+

1

BT

,

wherein B is a bandwidth of the received PM signal and T is a bit interval of the received PM signal.

5. The method of claim 1 wherein determining the phase error includes accessing, using the k data bits, a lookup table.

6. The method of claim 5 wherein determining the phase error further comprises inverting an output of the lookup table when the most recent data bit is one of an in-phase or a quadrature data bit.

7. The method of claim 1 wherein determining the phase error based on the k data bits comprises correlating the k data bits except the most recent data bit with a derivative with respect to phase of a conjugate of a reconstructed waveform.

8. The method of claim 7 wherein the derivative with respect to the phase is stored in a lookup table.

9. A circuit to correct a phase of a phase modulated (PM) signal, comprising:

a first circuit branch wherein a primary phase shifter, a register, one of an algorithm sub-circuit and a lookup table sub-circuit, and a loop phase shifter are arranged in electrical series, in that order;

a second circuit branch having an input in parallel with the first circuit branch, wherein a delay block and the loop phase shifter are arranged in electrical series, in that order;

the register for storing at least two data bits sampled from the PM signal; and

the loop phase shifter having an output coupled to an input of the primary phase shifter.

10. The circuit of claim 9 wherein the at least two data bits comprises a series that alternates between an in-phase bit and a quadrature bit.

11. The circuit of claim 10 wherein the first circuit branch further comprises a complement block disposed between the loop phase shifter and the one of the algorithm sub-circuit and the lookup table sub-circuit.

12. The circuit of claim 9 wherein the at least two data bits comprises

k

=

n

(

1

+

1

BT

)

data bits, wherein n is a number of samples per bit interval that is greater than or equal to one, B is a bandwidth of the PM signal and T is a bit interval of the PM signal.

13. The circuit of claim 9 wherein the one of the algorithm sub-circuit and the lookup table sub-circuit produces the phase correction by correlating all data bits in the register, except the most recent data bit, with a derivative with respect to phase of a conjugate of a waveform reconstructed from the PM signal.

Assignments (2)
CHANGE OF NAME Recorded Apr 11, 2023
From: L-3 COMMUNICATIONS CORPORATION
To: L3 TECHNOLOGIES, INC.
Reel/Frame 063295/0788 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2003
From: KINGSTON, SAMUEL C.; HADDADIN, OSAMA SAMI; MCINTIRE, WILLIAM K.
To: L-3 COMMUNICATIONS CORPORATION
Reel/Frame 014425/0337 →