IP Library Granted Patent US 6,993,447
Granted Patent B2
US 6,993,447 · App. 10/647,221 · Granted Jan 31, 2006

System LSI

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Quick Facts
Patent No.
US 6,993,447
App. No.
10/647,221
Granted
Jan 31, 2006
Kind
B2
Abstract

A system LSI includes a plurality of circuit blocks; a first power supply terminal, which is connected to a first circuit block; and a second power supply terminal, which is connected to a second circuit block. A first level of test voltage is applied from the first power supply terminal to the first circuit block for a predetermined period of time whereby the first circuit block is tested in operation. A second level of test voltage is applied from the second power supply terminal to the second circuit block for a predetermined period of time whereby the second circuit block is tested in operation independently from the first circuit block.

Claims (12)

1. A system large scale integration (LSI), comprising:

first, second and third circuit blocks, each circuit block being located on a wafer;

a first power supply terminal located on the wafer and supplied with a first power supply voltage for test, wherein the first power supply voltage has a first voltage level and has a second voltage level which is different from the first voltage level;

a first power supply line located on the wafer, which surrounds the first, second and third circuit blocks, and which is connected to the first power supply terminal and the first and second circuit blocks;

a second power supply terminal located on the wafer and supplied with a second power supply voltage for test, wherein the second power supply voltage has the first voltage level and has a third voltage level which is different from the first and second voltage levels; and

a second power supply line located on the wafer, which surrounds the first, second and third circuit blocks, and which is connected to the second power supply terminal and the third circuit block.

2. A system LSI according to claim 1 , wherein the first and second circuit blocks are tested on the wafer before fabrication of the system LSI is completed.

3. A system LSI according to claim 1 , further comprising:

a switching circuit, connected to the second circuit block and the first and second power supply lines, that couples either one of the first and second power supply lines to the second circuit block.

4. A system LSI according to claim 3 , wherein the first power supply line is surrounded by the second power supply line.

5. A system LSI according to claim 1 , wherein the first power supply line is surrounded by the second power supply line.

6. A system LSI according to claim 5 , wherein the first, second and third circuit blocks are tested on the wafer before fabrication of the system LSI is completed.

Assignments (3)
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
CHANGE OF NAME Recorded Dec 24, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022052/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2003
From: YAMASAKI, YOSHIHIRO
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 014483/0360 →