Manufacturing method for bipolar gate CMOS semiconductor device
View Patent ↗A manufacturing method for a bipolar gate CMOS semiconductor device is provided that eliminates a masking process for P-type polycrystalline silicon. An N-type polycrystalline silicon region is selectively formed in polycrystalline silicon constituting a gate electrode through predeposition using an insulating film as a mask, after which the insulating film is removed to implant P-type impurity ions into the entire surface to form a P-type polycrystalline silicon region.
1. A manufacturing method for a semiconductor device characterized by comprising:
a step of forming an element isolation region and a gate insulating film on a semiconductor substrate;
a step of forming a polycrystalline silicon film, for subsequently forming a gate electrode on the element isolation region and the gate insulating film;
a step of forming an insulating film on the polycrystalline silicon film;
a step of patterning the insulating film so as to open a region other than a region subsequently serving as a PMOS;
a step of changing the region of the polycrystalline silicon film corresponding to an insulating film opening into an N-type region by heat treatment in a diffusion furnace in an N-type impurity atmosphere;
a step of removing the insulating film patterned; and
a step of doping a P-type impurity into an entire surface of the polycrystalline silicon film through an ion implantation.
2. A manufacturing method for a semiconductor device according to claim 1 , further comprising forming a high melting point metal silicide including a tungsten silicide, a molybdenum silicide, or a titanium silicide, on the polycrystalline silicon.
3. A manufacturing method for a semiconductor device according to claim 1 , wherein the polycrystalline silicon film has a thickness of 50 nm to 400 nm.
4. A manufacturing method for a semiconductor device according to claim 1 , wherein the insulating film has a thickness of 100 nm or more.
5. A manufacturing method for a semiconductor device according to claim 1 , wherein the N-type polycrystalline silicon has an impurity concentration of 1×10 20 /cm 3 or more.
6. A manufacturing method for a semiconductor device according to claim 1 , wherein a dosage of a P-type impurity ion in the ion implantation is 1×10 15 /cm 2 or more.