IP Library Granted Patent US 6,879,037
Granted Patent B2
US 6,879,037 · App. 10/648,425 · Granted Apr 12, 2005

Semiconductor device and a method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,879,037
App. No.
10/648,425
Granted
Apr 12, 2005
Kind
B2
Abstract

A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.

Claims (11)

1. A semiconductor device comprising:

a lead frame having a chip supporting portion and a plurality of leads;

a first semiconductor chip and a second semiconductor chip each having an integrated circuit and bonding pads formed on a main surface thereof, and a rear surface opposing to said main surface;

a plurality of bonding wires connecting one ends of said plurality of leads with said bonding pads of said first and second semiconductor chips respectively; and

a resin body sealing said first and second semiconductor chips, said plurality of bonding wires and said chip supporting portion and portions of said plurality of leads,

wherein said first semiconductor chip is mounted on one surface of said chip supporting portion by an adhesive layer, while said second semiconductor chip is mounted on the other surface of said chip supporting portion by an adhesive layer such that said main surfaces of said first and second semiconductor chips are faced to each other, and

wherein said plurality of bonding wires are formed such that a peak height of each of said plurality of bonding wires is within a total thickness of said chip supporting portion, said adhesive layers and said first and second semiconductor chips in a thickness direction of said chip supporting portion.

2. A semiconductor device according to claim 1 , wherein said plurality of bonding wires include a first group of bonding wires for said first semiconductor chip and a second group of bonding wires for said second semiconductor chip, wherein said second group of bonding wires are connected to one surface of said plurality of leads, and wherein said first group of bonding wires are connected to the other surface of said plurality of leads.

3. A semiconductor device according to claim 1 , wherein said resin body has an upper surface, a lower surface opposing said upper surface and a pair of opposed side surfaces between said upper and lower surfaces, wherein said first group of bonding wires are connected with said plurality of leads protruding outwardly from one of said pair of opposed side surfaces of said resin body, and wherein said second group of bonding wires are connected with said plurality of leads protruding outwardly from the other of said pair of opposed side surfaces of said resin body.

4. A semiconductor device according to claim 3 , wherein each of said first and second semiconductor chips includes a flash memory circuit, and wherein arrangements of said bonding pads and electrical function of said first and second semiconductor chips are identical to each other.

5. A semiconductor device according to claim 4 , wherein each of said first and second semiconductor chips has a rectangular shape, and wherein said bonding pads of each of said first and second semiconductor chips are arranged along one of paired opposed edges of said first and second semiconductor chips.

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER AND CHANGE OF NAME Recorded Jul 29, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024755/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2004
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 015447/0003 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2004
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 015448/0531 →