Thin film transistor array panel and manufacturing method thereof
View Patent ↗Gate lines and a gate shorting bar connected to the gate lines, which include lower and upper films, are formed on a substrate. A gate insulating layer, semiconductors, and ohmic contacts are formed in sequence. Data lines and a data shorting bar connected to the data lines, which include lower and upper films, are formed thereon. A passivation layer is formed on the data lines and the data shorting bar. The passivation layer and the gate insulating are patterned to form contact holes exposing the lower films of the gate lines and the data lines. Connecting portions of the gate lines and the data lines for connection with driving circuits are locate opposite the shorting bars with respect to the contact holes.
1. A thin film transistor array panel comprising:
a plurality of gate lines formed on an insulating substrate;
a gate insulating layer formed on the gate lines;
a semiconductor layer formed on the gate insulating layer;
a plurality of data lines formed at least in part on the semiconductor layer;
a plurality of drain electrodes formed at least in part on the semiconductor layer;
a plurality of pixel electrodes connected to the drain electrodes; and
a plurality of conductive lines, each conductive line connected to one of the gate lines and the data lines and including first and second portions having different resistances.
2. The thin film transistor array panel of claim 1 , wherein each conductive line includes a lower film and an upper film having resistivity lower than the lower film and the first portion of each conductive line does not include the upper film.
3. The thin film transistor array panel of claim 2 , further comprising a passivation layer disposed between the data lines and the pixel electrodes.
4. The thin film transistor array panel of claim 3 , wherein the passivation layer has a plurality of first contact holes exposing the first portions of the conductive lines.
5. The thin film transistor array panel of claim 4 , wherein the first contact holes expose edges of the first portions of the conductive lines.
6. The thin film transistor array panel of claim 4 , wherein the passivation layer further has a plurality of second and third contact holes exposing portions of the gate lines and the data lines, respectively.
7. The thin film transistor array panel of claim 6 , further comprising a plurality of contact assistants formed of the same layer as the pixel electrodes and connected to the gate lines and the data lines through the second and the third contact holes, respectively.
8. The thin film transistor array panel of claim 4 , further comprising a plurality of protective members formed of the same layer as the pixel electrodes and covering the first portions of the conductive lines.
9. The thin film transistor array panel of claim 1 , further comprising a plurality of ohmic contacts disposed between the semiconductor layer and the data lines.
10. The thin film transistor array panel of claim 1 , wherein the semiconductor layer has substantially the same planar shape as the data lines and the drain electrodes except for portions located between the data lines and the drain electrodes.
11. The thin film transistor array panel of claim 1 , further comprising a shorting bar connected to the conductive lines.
12. The thin film transistor array panel of claim 1 , wherein the conductive lines extend to an edge of the thin film transistor array panel.