IP Library Granted Patent US 7,120,736
Granted Patent B2
US 7,120,736 · App. 10/649,687 · Granted Oct 10, 2006

Storage unit and circuit for shaping communication signal

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Quick Facts
Patent No.
US 7,120,736
App. No.
10/649,687
Granted
Oct 10, 2006
Kind
B2
Abstract

The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing data, wherein at least two of the disk drives input data to and output it from the disk control portion at different communication speeds. Further, the storage unit has a plurality of communication paths provided to connect at least one of the disk drives in such a manner as to constitute a loop defined by the FC-AL fiber channel standards, so that the communication speeds can be set differently for these different communication paths.

Claims (49)

1. A storage unit comprising:

a channel control portion for receiving a data input/output request;

a cache memory for storing data;

a disk control portion for performing input/output processing on data in accordance with said data input/output request;

a plurality of disk drives for storing data,

wherein at least two of said disk drives input data to and output data from said disk control portion at different communication speeds relative to the communication speeds of the others of said disk drives,

a generation portion for generating a clock signal by using a pulse signal transferred for communication between said disk control portion and said disk drives;

an identification portion for identifying a frequency of said pulse signal;

a frequency division portion for dividing a frequency of said clock signal at a frequency division ratio that corresponds to a frequency of said pulse signal; and

a synchronization portion for synchronizing said pulse signal with a clock signal having said divided frequency,

wherein said identification portion comprises:

a charge accumulation portion for outputting a voltage that corresponds to a quantity of charge accumulated therein,

a charge quantity variation portion for varying said quantity of said charge accumulated in said charge accumulation portion, at a certain variation rate,

a charge quantity variation suppression portion for inhibiting said variation only during a certain lapse of time each time a signal level of said pulse signal is switched,

a signal output portion for outputting a signal that corresponds to whether said voltage output from said charge accumulation portion satisfies a criterion,

a time measurement portion for measuring a lapse of time that has elapsed since said quantity of said charge accumulated in said charge accumulation portion started to vary, and

a frequency identification portion for identifying said frequency based on said lapse of time from a moment when said quantity of said charge started to vary to a moment when said signal that indicates that said voltage of said charge accumulation portion satisfies said criterion was output.

2. The storage unit according to claim 1 , wherein said storage unit has a plurality of communication paths for connecting at least one of said disk drives in such a manner as to constitute a loop defined by the Fibre Channel (FC) Standards; and

each of said communication speeds is different for each of said communication paths.

3. The storage unit according to claim 1 , wherein said communication is performed through a communication path which is provided to connect said disk control portion and at least one of said disk drives in such a manner as to constitute a loop defined by the FC Arbitrated Loop (AL) Standards.

4. The storage unit according to claim 1 , wherein said communication is performed through a communication path provided to connect said disk control portion and at least one of said disk drives in such a manner as to constitute a loop defined by the FC-AL Standards.

5. The storage unit according to claim 1 , wherein said charge quantity variation portion comprises a charging portion for charging said charge accumulation portion; and

said charge quantity variation suppression portion comprises:

a pulse deviation signal generation portion for generating a pulse deviation signal having its phase as shifted with respect to that of said pulse signal by certain time; and

a discharging portion for discharging said charge accumulation portion only in a period when there is a potential difference between said pulse signal and said pulse deviation signal.

6. The storage unit according to claim 1 , further comprising:

a communication specifications decision portion for deciding whether said pulse signal satisfies predetermined communication specifications, when said pulse signal is read in a period of said clock signal.

7. The storage unit according to claim 6 , wherein said communication is performed through a communication path which is provided to connect said disk control portion and at least one of said disk drives in such a manner as to constitute a loop defined by the FC-AL Standards.

8. A circuit for shaping a communication signal in a storage unit according to claim 1 , comprising:

a generation portion for generating a clock signal by using a pulse signal transferred communication between said disk control portion and said disk drives;

an identification portion for identifying a frequency of said pulse signal;

a frequency division circuit for dividing a frequency of said clock signal at a frequency division ratio that corresponds to a frequency of said pulse signal; and

a synchronization portion for synchronizing said pulse signal with said clock signal having said divided frequency.

9. The circuit according to claim 8 , wherein said identification portion comprises:

a charge accumulation portion for outputting a voltage that corresponds to a quantity of charge accumulated therein;

a charge quantity variation portion for varying said quantity of said charge accumulated in said charge accumulation portion, at a certain variation rate;

a charge quantity variation suppression portion for inhibiting said variation only during a certain lapse of time each time a signal level of said pulse signal is switched;

a signal output portion for outputting a signal that corresponds to whether said voltage output from said charge accumulation portion satisfies a criterion;

a time measurement portion for measuring a lapse of time that has elapsed since said quantity of said charge accumulated in said charge accumulation portion started to vary; and

a frequency identification portion for identifying said frequency based on said lapse of time from a moment when said quantity of said charge started to vary to a moment when said signal that indicates that said voltage of said charge accumulation portion satisfies said criterion was output.

10. The circuit according to claim 9 , wherein; said charge quantity variation portion comprises a charging portion for charging said charge accumulation portion; and

said charge quantity variation suppression portion comprises:

a pulse deviation signal generation portion for generating a pulse deviation signal having its phase as shifted with respect to that of said pulse signal by certain time; and

a discharging portion for discharging said charge accumulation portion only in a period when there is a potential difference between said pulse signal and said pulse deviation signal.

11. A circuit for shaping a communication signal in a storage unit according to claim 1 , comprising:

a generation portion for generating a clock signal by using a pulse signal transferred communication between said disk control portion and said disk drives;

a communication specifications decision portion for deciding whether said pulse signal satisfies specifications of said communication, when said pulse signal is read in a period of said clock signal;

a frequency division portion for dividing a frequency of said clocks signal in accordance with a result of said decision; and

a synchronization portion for synchronizing said pulse signal with said clock signal having said divided frequency.

Assignments (3)
CHANGE OF NAME Recorded Oct 5, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044127/0735 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2013
From: HITACHI, LTD.
To: GOOGLE INC.
Reel/Frame 030555/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2003
From: MATSUSHIGE, HIROMI; SUZUKI, HIROSHI; OGAWA, MASATO; YOKOYAMA, TOMOKAZU; SAKAKIBARA, YASUHIRO
To: HITACHI LTD.
Reel/Frame 014756/0307 →