Recursive decoder for switching between normalized and non-normalized probability estimates
View Patent ↗The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.
1. A decoder for decoding encoded data, the decoder comprising:
a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculate probability estimates for said symbols in a next iterative state;
normalizing means for normalizing said calculated probability estimates to provide normalized probability estimates;
a switch arranged to receive both said calculated probability estimates and said normalized probability estimates, an output of the switch being coupled to the input of the processor;
wherein the switch is arranged to switch between the calculated probability estimates and the normalized probability estimates depending on the iterative state.
2. The decoder according to claim 1 wherein said decoder comprises a MAP algorithm wherein the probability estimates are α and β values.
3. The decoder according to claim 1 wherein said decoder has eight iterative states for each received symbol block.
4. The decoder according to claim 1 wherein the ratio between said calculated probability estimates and said normalized probability estimates is 7:1.
5. The decoder according to claim 1 wherein said switch is a multiplexer.
6. The decoder according to claim 1 further comprising pipeline registers between said processor and said normalizing function.
7. A turbo decoder comprising the decoder according to claim 1 .
8. A decoder for decoding encoded data, the decoder comprising:
a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculate probability estimates for said symbols in a next iterative state;
normalizing means coupled to the processor for normalizing said calculated probability estimates to provide normalized probability estimates;
pipelining means between the processor and the normalizing means for providing non-normalized probability estimates; and
switching means for receiving both said calculated probability estimates and said normalized probability estimates, an output of the switching means being coupled to the input of the processor;
wherein the switching means is arranged to switch between the calculated probability estimates and the normalized probability estimates depending on the iterative state.
9. The decoder according to claim 8 wherein said pipelining means is a pipeline register coupled between outputs of said processor and inputs of said normalizing means.