Unified shared pipeline allowing deactivation of RISC/DSP units for power saving
View Patent ↗An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.
1. An integrated circuit comprising:
a reduced instruction set computer (RISC) controller to execute RISC instructions;
one or more digital signal processing (DSP) units to execute DSP instructions; and
a unified pipeline controller coupled to the RISC controller and the one or more DSP units, the unified pipeline controller to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified pipeline controller comprising a first portion of stages and a second portion of stages, the first portion providing a first depth for decoding and initiating the RISC instructions when the DSP instructions are inactive, and the first portion and the second portion together providing a second depth for decoding and initiating the DSP instructions when the RISC instructions are inactive.
2. The integrated circuit of claim 1 , wherein
the unified pipeline controller reduces decode circuitry to conserve power otherwise needed to process RISC instructions and DSP instructions.
3. The integrated circuit of claim 1 , wherein the unified pipeline controller includes:
a loop buffer to store instructions in a program loop and to decode and initiate execution of the instructions stored therein while in the program loop.
4. The integrated circuit of claim 3 , wherein
the loop buffer avoids continuous fetching of the instructions in the program loop from memory to conserve power.
5. The integrated circuit of claim 1 , wherein
the first and second depths of the unified pipeline controller allow for deactivating the RISC controller when the DSP instructions are executed and deactivating the one or more DSP units when the RISC instructions are executed.
6. The integrated circuit of claim 1 , wherein the first portion of the unified pipeline controller comprises a first sub-portion to provide for fetching of instructions for both RISC instructions and DSP instructions.
7. The integrated circuit of claim 6 , wherein the first portion of the unified pipeline controller comprises a second sub-portion to provide for decoding and performance of operation for RISC instructions, and to provide for decoding for DSP instructions.
8. The integrated circuit of claim 7 , wherein the first portion of the unified pipeline controller comprises a third sub-portion to provide for completion of execution for RISC instructions, and to provide for memory access for DSP instructions.
9. The integrated circuit of claim 8 , wherein the second portion of the unified pipeline controller provides for execution and writeback for DSP instructions.
10. An integrated circuit comprising:
a reduced instruction set computer (RISC) controller to execute RISC instructions;
one or more digital signal processing (DSP) units to execute DSP instructions; and
a unified pipeline controller coupled to the RISC controller and the one or more DSP units, the unified pipeline controller with minimal decode circuitry to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified pipeline controller comprising a first portion of stages and a second portion of stages, the first portion providing a first depth for decoding and initiating the RISC instructions when the DSP instructions are inactive, and the first portion and the second portion together providing a second depth for decoding and initiating the DSP instructions when the RISC instructions are inactive.
11. The integrated circuit of claim 10 , wherein:
the minimal decode circuitry of the unified pipeline controller to conserve power.
12. The integrated circuit of claim 10 , wherein the unified pipeline controller includes:
a loop buffer to store instructions in a program loop and to decode and initiate execution of the instructions stored therein while in the program loop.
13. The integrated circuit of claim 12 , wherein
with the instructions of the program loop stored in the loop buffer, continuous fetching of instructions from memory is avoided to conserve power.
14. The integrated circuit of claim 10 , wherein
the first and second depths of the unified pipeline controller allow for deactivating the RISC controller when the DSP instructions are executed and deactivating the one or more DSP units when the RISC instructions are executed.
15. The integrated circuit of claim 10 , wherein the first portion of the unified pipeline controller comprises one or more of instruction fetch stages, instruction decode stages, and memory access stages.
16. The integrated circuit of claim 15 , wherein the second portion of the unified pipeline controller comprises one or more of execution stages and writeback stages.
17. An integrated circuit comprising:
a reduced instruction set computer (RISC) controller to execute RISC instructions;
one or more digital signal processing (DSP) units to execute DSP instructions; and
a unified pipeline controller coupled to the RISC controller and the one or more DSP units, the unified pipeline controller to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified pipeline controller comprising a first portion of stages and a second portion of stages, the first portion providing a first depth for decoding and initiating the RISC instructions when the DSP instructions are inactive, and the first portion and the second portion together providing a second depth for decoding and initiating the DSP instructions when the RISC instructions are inactive, the unified pipeline controller including:
a loop buffer to store DSP instructions in a program loop and to decode and initiate execution of the DSP instructions stored therein while in the program loop.
18. The integrated circuit of claim 17 , wherein with the instructions of the program loop stored in the loop buffer, continuous fetching of instructions from memory is avoided to conserve power.
19. The integrated circuit of claim 17 , wherein the unified pipeline controller has minimal decode circuitry to decode and initiate execution of the RISC instructions and the DSP instructions and to conserve power.
20. The integrated circuit of claim 17 , wherein
the first and second depths of the unified pipeline controller allow for deactivating the RISC controller when the DSP instructions are executed and deactivating the one or more DSP units when the RISC instructions are executed.
21. The integrated circuit of claim 17 , wherein RISC instructions are processed by the first portion of the unified pipeline controller, and wherein DSP instructions are processed by both the first portion and the second portion of the unified pipeline controller.