Disk drive employing enhanced instruction cache management to facilitate non-sequential immediate operands
View Patent ↗A disk drive is disclosed for executing a program comprising a plurality of instructions. The disk drive comprises a primary memory for storing the instructions, and a cache memory for caching the instructions. The cache management is enhanced by not re-filling the cache due to accessing a non-sequential immediate operand.
1. A disk drive for executing a program comprising a plurality of instructions, the disk drive comprising:
(a) a disk;
(b) a head actuated over the disk;
(c) a primary memory for storing a plurality of the instructions;
(d) a cache memory for caching a subset of the instructions stored in the primary memory;
(e) a microprocessor for executing the instructions; and
(f) a memory controller for transferring the instructions to the microprocessor, wherein:
the memory controller transfers an instruction from the cache memory to the microprocessor if the instruction is stored in the cache memory;
the memory controller transfers the instruction from the primary memory to the microprocessor if the instruction is not stored in the cache memory; and
the memory controller replaces at least one instruction stored in the cache memory with an instruction stored in the primary memory if:
the memory controller transfers a first instruction and a second instruction to the microprocessor;
the first instruction and second instruction have sequential addresses; and
the second instruction is transferred from the primary memory.
2. The disk drive as recited in claim 1 , wherein the first instruction is transferred from the cache memory.
3. The disk drive as recited in claim 1 , wherein the first instruction is transferred from the primary memory.
4. The disk drive as recited in claim 1 , wherein:
(a) the microprocessor comprises a register; and
(b) the instructions comprise a load instruction for loading a non-sequential immediate operand into the register.
5. The disk drive as recited in claim 4 , wherein:
(a) the cache memory stores the load instruction, a plurality of instructions preceding the load instruction, and a plurality of instructions following the load instruction exclusive of the non-sequential immediate operand;
(b) when the microprocessor executes the load instruction, the memory controller transfers the non-sequential immediate operand from the primary memory to the microprocessor; and
(c) the memory controller does not replace an instruction in the cache memory with an instruction from the primary memory due to transferring the non-sequential immediate operand from the primary memory to the microprocessor.
6. The disk drive as recited in claim 1 , wherein:
(a) the microprocessor comprises a program counter for tracking an execution sequence of the instructions;
(b) the instructions comprise a branch instruction for loading an address into the program counter;
(c) after the microprocessor executes the branch instruction, the memory controller transfers a sequential instruction from the primary memory to the microprocessor; and
(d) the memory controller replaces at least one instruction in the cache memory with an instruction from the primary memory due to transferring the sequential instruction from the primary memory to the microprocessor.
7. A method of executing a program in a disk drive, the program comprising a plurality of instructions, the disk drive comprising a disk, a head actuated over the disk, a primary memory for storing the plurality of the instructions, a cache memory for caching a subset of the instructions stored in the primary memory, and a microprocessor for executing the instructions, the method comprising the steps of:
(a) transferring an instruction from the cache memory to the microprocessor if the instruction is stored in the cache memory;
(b) transferring the instruction from the primary memory to the microprocessor if the instruction is not stored in the cache memory; and
(c) replacing at least one instruction stored in the cache memory with an instruction stored in the primary memory if:
a first instruction and a second instruction are transferred to the microprocessor;
the first instruction and second instruction have sequential addresses; and
the second instruction is transferred from the primary memory.
8. The method as recited in claim 7 , wherein the first instruction is transferred from the cache memory.
9. The method as recited in claim 7 , wherein the first instruction is transferred from the primary memory.
10. The method as recited in claim 7 , wherein:
(a) the microprocessor comprises a register; and
(b) the instructions comprise a load instruction for loading a non-sequential immediate operand into the register.
11. The method as recited in claim 10 , further comprising the steps of:
(a) storing in the cache memory the load instruction, a plurality of instructions preceding the load instruction, and a plurality of instructions following the load instruction exclusive of the non-sequential immediate operand;
(b) when the microprocessor executes the load instruction, transferring the non-sequential immediate operand from the primary memory to the microprocessor without replacing an instruction in the cache memory with an instruction from the primary memory due to the transfer.
12. The method as recited in claim 7 , wherein:
(a) the microprocessor comprises a program counter for tracking an execution sequence of the instructions;
(b) the instructions comprise a branch instruction for loading an address into the program counter;
(c) after the microprocessor executes the branch instruction, further comprising the step of transferring a sequential instruction from the primary memory to the microprocessor; and
(d) replacing at least one instruction in the cache memory with an instruction from the primary memory due to transferring the sequential instruction from the primary memory to the microprocessor.