Pulse generating circuit and semiconductor device provided with same
View Patent ↗A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and operating to output a first voltage changing from a high level towards a low level based on a first time constant according to a one-shot pulse, a second voltage outputting section having a second delay circuit and operating to output a second voltage changing from a low level towards a high level based on a second time constant according to the one-shot pulse, and a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting the one-shot pulse to a cross time point when the first voltage coincides with the second voltage.
1. A pulse generating circuit comprising:
a first voltage outputting section comprising:
a first delay circuit comprising a first resistor and a first capacitor and operating to output a first output voltage that changes from a first voltage towards a second voltage based on a first time constant according to a one-shot pulse; and
a first transistor responsive to the one-shot pulse for allowing the first capacitor to charge to the first voltage within a charging time period less than a width of the one-shot pulse;
a second voltage outputting section comprising:
a second delay circuit comprising a second resistor and a second capacitor and operating to output a second output voltage that changes from said second voltage towards said first voltage based on a second time constant according to said one-shot pulse; and
a second transistor responsive to the one-shot pulse for allowing the second capacitor to discharge to the second voltage within a discharging time period less than the width of the one-shot pulse; and
a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting said one-shot pulse to a cross time point when said first output voltage has the same value as said second output voltage.
2. The pulse generating circuit according to claim 1 , wherein said differential circuit comprises an input stage which is made up of a first conductive type of MOS transistors and a current mirror circuit which is made up of a second conductive type of MOS transistors.
3. The pulse generating circuit according to claim 2 , wherein threshold voltages of said first conductive type of MOS transistors are set to be equal to each other.
4. The pulse generating circuit according to claim 2 , wherein said first conductive type of MOS transistors comprise n-channel MOS transistors, and a threshold voltage of each of said n-channel MOS transistors is 0 (zero) V or more and a cross-point voltage level or less, said cross-point voltage level being defined as a level of said first output voltage and said second output voltage at said cross time point.
5. The pulse generating circuit according to claim 2 , wherein said first conductive type of MOS transistors comprise p-channel MOS transistors, and an absolute value of a threshold voltage of each of said p-channel MOS transistors is a cross-point voltage level or more, and a level of a source voltage or less, said cross-point voltage level being defined as a level of said first output voltage and said second output voltage at said cross time point; and
wherein the source voltage is an input to the p-channel MOS transistors.
6. The pulse generating circuit according to claim 1 , wherein said one-shot pulse is active high.
7. The pulse generating circuit according to claim 1 , wherein said one-shot pulse is active low.
8. The pulse generating circuit according to claim 1 , wherein said first time constant is equal to said second time constant.
9. A semiconductor device provided with a pulse generating circuit comprising:
a first voltage outputting section comprising:
a first delay circuit comprising a first resistor and a first capacitor and operating to output a first output voltage that changes from a first voltage towards a second voltage based on a first time constant according to a one-shot pulse; and
a first transistor responsive to the one-shot pulse for allowing the first capacitor to charge to the first voltage within a charging time period less than a width of the one-shot pulse;
a second voltage outputting section comprising:
a second delay circuit comprising a second resistor and a second capacitor and operating to output a second output voltage that changes from said second voltage towards said first voltage based on a second time constant according to said one-shot pulse; and
a second transistor responsive to the one-shot pulse for allowing the second capacitor to discharge to the second voltage within a discharging time period less than the width of the one-shot pulse; and
a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting said one-shot pulse to a cross time point when said first output voltage has the same value as said second output voltage.
10. The semiconductor device according to claim 9 , wherein said differential circuit comprises an input stage which is made up of a first conductive type of MOS transistors and a current mirror circuit which is made up of a second conductive type of MOS transistors.
11. The semiconductor device according to claim 10 , wherein threshold voltages of said first conductive type of MOS transistors are set to be equal to each other.
12. The semiconductor device according to claim 10 , wherein said first conductive type of MOS transistors comprise n-channel MOS transistors, and a threshold voltage of each of said n-channel MOS transistors is 0 (zero) V or more and a cross-point voltage level or less, said cross-point voltage level being defined as a level of said first output voltage and said second output voltage at said cross time point.
13. The semiconductor device according to claim 10 , wherein said first conductive type of MOS transistors comprise p-channel MOS transistors, and an absolute value of a threshold voltage of each of said p-channel MOS transistors is a cross-point voltage level or more, and a level of a source voltage or less, said cross-point voltage level being defined as a level of said first output voltage and said second output voltage at said cross time point; and
wherein the source voltage is an input to the p-channel MOS transistors.
14. The pulse generating circuit according to claim 9 , wherein said one-shot pulse is active high.
15. The pulse generating circuit according to claim 9 , wherein said one-shot pulse is active low.
16. The pulse generating circuit according to claim 9 , wherein said first time constant is equal to said second time constant.