Array substrate for use in LCD device and method of fabricating same
View Patent ↗A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase a gate line over a said substrate; a data line over the said substrate being perpendicular to the gate line; a passivation layer covering the data line, the passivation layer divided into a residual passivation layer and a etched passivation layer; a doped amorphous silicon layer formed under the data line and corresponding in size to the data line; a pure amorphous silicon layer formed under the doped amorphous silicon layer and having a over-etched portion in the peripheral portions, wherein the over-etched portion is over-etched from the edges of the residual passivation layer toward the inner side; an insulator layer under the pure amorphous silicon layer; a TFT formed near the crossing of the gate line and the data line; and a pixel electrode overlapping the data line and contacting the TFT.
1. A thin film transistor substrate for use in a LCD device, comprising:
a substrate;
a gate line over the substrate;
a data line over the substrate, the data line being perpendicular to the gate line;
a passivation layer pattern covering the data line, the passivation layer corresponding to and disposed along the data line;
a doped amorphous silicon layer formed under the data line and corresponding in size to the data line;
a pure amorphous silicon layer formed under the doped amorphous silicon layer and having an over-etched portion in peripheral portions, wherein the over-etched portion is over-etched from edges of the passivation layer pattern toward an inner side;
an insulator layer under the pure amorphous silicon layer;
a TFT formed near a crossing of the gate line and the data line; and
a pixel electrode contacting the TFT,
wherein the over-etched portion is over-etched from edges of the passivation layer pattern toward an inner side to be an empty space.
2. The thin film transistor substrate according to claim 1 , wherein the pixel electrode is made of the transparent conductive material.
3. The thin film transistor substrate according to claim 2 , wherein the transparent conductive material is selected from a group consisting of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).
4. The thin film transistor substrate according to claim 1 , wherein a portion of the pixel electrode overlaps the over-etched portion of the pure amorphous silicon layer.
5. A thin film transistor substrate for use in a LCD device, comprising:
a substrate;
a gate line over the substrate;
a data line over the substrate, the data line being perpendicular to the gate line;
a TFT formed on the substrate, the TFT including a gate electrode, a source electrode, and a drain electrode;
a passivation layer pattern covering the TFT and the data line, the passivation layer pattern corresponding to and disposed along the data line;
a doped amorphous silicon layer formed under the source and drain electrodes;
a pure amorphous silicon layer formed under the doped amorphous silicon layer and having an over-etched portion at a peripheral portion, wherein the over-etched portion is over-etched from an edge of the passivation layer pattern toward an inner side;
an insulator layer under the pure amorphous silicon layer; and
a pixel electrode disposed on the passivation layer,
wherein the pixel electrode contacting an upper portion and a side portion of the drain electrode and the over-etched portion is over-etched from edges of the passivation layer pattern toward an inner side to be an empty space.