Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof
View Patent ↗Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
1. A thin film transistor array panel comprising:
a gate conductive layer formed on an insulating substrate;
a gate insulating layer on the gate conductive layer;
a semiconductor layer on the gate insulating layer;
a data conductive layer formed at least in part on the semiconductor layer and comprising a source electrode and a drain electrode separated from each other;
a passivation layer formed on the data conductive layer; and
an IZO conductive layer formed on the passivation layer,
wherein at least one of the gate conductive layer and the data conductive layer includes a dry-etchable lower film and an upper film formed on the lower film, the upper film including Al or Al alloy and having edges located on the lower film,
the IZO conductive layer contacts the lower film and a top surface of the upper film, and
the semiconductor layer has substantially the same planar shape as the data conductive layer except for a portion located between the source electrode and the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein edges of the lower film are located near edges of the upper film adjacent thereto.
3. The thin film transistor array panel of claim 1 , wherein the IZO conductive layer contacts an edge of the lower film.
4. The thin film transistor array panel of claim 1 , wherein the distance between edges of the lower film and edges of the upper film adjacent thereto is substantially uniform.
5. The thin film transistor array panel of claim 1 , wherein the lower film comprises Cr.
6. The thin film transistor array panel of claim 5 , wherein the lower film has a thickness equal to or less than about 500 Å.
7. The thin film transistor array panel of claim 1 , wherein the IZO conductive layer comprises a pixel electrode contacting the drain electrode, a gate contact assistant contacting a portion of the gate conductive layer, and a data contact assistant contacting a portion of the data line.
8. The thin film transistor array panel of claim 1 , wherein the edges of the upper film include at least opposing edges defining the upper film in a longitudinal direction.
9. The thin film transistor array panel of claim 1 , wherein the edges of the upper film include at least opposing edges defining the upper film in a transverse direction.
10. The thin film transistor array panel of claim 1 , wherein the edges of the upper film include all edges defining the upper film.
11. The thin film transistor array panel of claim 1 , wherein the semiconductor layer has substantially the same planar shape as the lower film of the data conductive layer except for a portion located between the lower film of the source electrode and the lower film of the drain electrode.
12. The thin film transistor array panel of claim 11 , further comprising an ohmic contact layer interposed between the semiconductor layer and the lower film of the source electrode and the lower film of the drain electrode and having substantially the same planar shape as the semiconductor layer.