Input terminal with combined logic threshold and reset function
View Patent ↗A circuit receives a first supply voltage on a first terminal where the first supply voltage is used to supply circuitry within the circuit. The circuit includes an input terminal receiving a first signal and an input circuit coupled to the input terminal. The first signal has a logical high value at a second voltage and a logical low value at a third voltage. The second voltage is used to establish a switching threshold of at least some of the input and output signals of the circuit. The input circuit provides a reset signal to circuitry within the circuit causing the circuitry to reset. The reset signal is asserted when the first signal on the input terminal has a logical low value and the third voltage comprises a voltage below a predetermined trigger threshold of the input circuit.
1. A circuit receiving a first supply voltage on a first terminal, the first supply voltage being used to supply circuitry within the circuit, the circuit comprising:
an input terminal receiving a first signal, the first signal having a logical high value at a second voltage and a logical low value at a third voltage, the second voltage being used to establish a switching threshold of at least some of the input and output signals of the circuit; and
an input circuit coupled to the input terminal, the input circuit providing a reset signal to circuitry within the circuit causing the circuitry to reset,
wherein the reset signal is asserted when the first signal on the input terminal has a logical low value and the third voltage comprises a voltage below a predetermined trigger threshold of the input circuit.
2. The circuit of claim 1 , wherein the input circuit comprises a buffer including an input terminal coupled to receive the first signal and an output terminal providing the reset signal and the predetermined trigger threshold comprises the trigger threshold of the buffer.
3. The circuit of claim 2 , wherein the buffer comprises an inverting buffer.
4. The circuit of claim 1 , wherein the input circuit comprises:
a level shifter coupled to receive the first signal and providing an output signal indicative of the logical state of the first signal and having a switching threshold based on the first supply voltage; and
a buffer including an input terminal coupled to receive the output signal of the level shifter and an output terminal providing the reset signal,
wherein the predetermined trigger threshold comprises the trigger threshold of the buffer.
5. The circuit of claim 4 , wherein the buffer comprises an inverting buffer.
6. The circuit of claim 2 , wherein the input circuit further comprises a logical OR gate having a first input terminal coupled to receive the output signal of the buffer and a second input terminal coupled to receive a power-on reset signal, the logical OR gate having an output terminal providing the reset signal.
7. A USB transceiver, comprising:
a first input terminal receiving a first supply voltage, the first supply voltage being used to supply circuitry within the transceiver;
a second input terminal receiving a first signal, the first signal having a logical high value at a second voltage and a logical low value at a third voltage, the second voltage being used to establish a switching threshold of at least some of the input and output signals of the transceiver; and
an input circuit coupled to the second input terminal, the input circuit providing a reset signal to circuitry within the transceiver causing the circuitry to reset,
wherein the reset signal is asserted when the first signal on the second input terminal has a logical low value and the third voltage comprises a voltage below a predetermined trigger threshold of the input circuit.
8. The USB transceiver of claim 7 , wherein the input circuit comprises a buffer including an input terminal coupled to receive the first signal and an output terminal providing the reset signal and the predetermined trigger threshold comprises the trigger threshold of the buffer.
9. The USB transceiver of claim 8 , wherein the buffer comprises an inverting buffer.
10. The USB transceiver of claim 7 , wherein the input circuit comprises:
a level shifter coupled to receive the first signal and providing an output signal indicative of the logical state of the first signal and having a switching threshold based on the first supply voltage; and
a buffer including an input terminal coupled to receive the output signal of the level shifter and an output terminal providing the reset signal,
wherein the predetermined trigger threshold comprises the trigger threshold of the buffer.
11. The USB transceiver of claim 10 , wherein the buffer comprises an inverting buffer.
12. The USB transceiver of claim 8 , wherein the input circuit further comprises a logical OR gate having a first input terminal coupled to receive the output signal of the buffer and a second input terminal coupled to receive a power-on reset signal, the logical OR gate having an output terminal providing the reset signal.