Data processing device
View Patent ↗A data processing device has an instruction decoder ( 1 ), a control logic unit ( 3 ), and ALU ( 4 ). The instruction decoder ( 1 ) decodes instruction codes of an arithmetic instruction. The control logic unit ( 3 ) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder ( 1 ) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU ( 4 ) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit ( 3 ).
1. A data processing device comprising:
an instruction decoder for decoding an instruction code in an arithmetic instruction;
a controller for detecting an effective data width of operation data to be processed for the arithmetic instruction based on the operation data and the decode result from the instruction decoder, and for determining an instruction execution cycle number which is the number of cycles of the execution of the instruction corresponding to the effective data width detected; and
an arithmetic operation unit for executing the arithmetic instruction with the number of cycles for the instruction execution determined by the controller.
2. The data processing device as claimed in claim 1 , wherein the instruction code of the arithmetic instruction includes instruction code information to control the instruction execution cycle number.
3. The data processing device as claimed in claim 2 , wherein whether or not the operation data include a sign is specified as the instruction code information.
4. The data processing device as claimed in claim 2 , wherein the upper limit value for a range of searching for use in the detection of the effective data width of the operation data is specified as the instruction code information.
5. The data processing device as claimed in claim 1 , further comprises a memory unit for storing process setting information, and
wherein the controller determines the instruction execution cycle number based on the process setting information read from the memory unit.
6. The data processing device as claimed in claim 5 , wherein a sign of the operation data is specified as the process setting information.
7. The data processing device as claimed in claim 5 , wherein an upper limit value of a searching range when detecting the effective data width of the operation data is specified as the process setting information.
8. The data processing device as claimed in claim 5 , wherein whether or not the effective data width of the operation data is determined based on the operation data is specified as the process setting information.
9. The data processing device as claimed in claim 5 , wherein whether instruction code information included in the instruction code is valid or invalid, is specified as the process setting information.
10. The data processing device as claimed in claim 1 , wherein the effective data width is bit length of the operation data.
11. The data processing device as claimed in claim 1 , wherein the decode result includes type of the instruction code, operation data type information and control information for controlling the instruction cycle.
12. The data processing device as claimed in claim 1 , further including a register device storing the operation data.