Granted Patent B2

US 7,225,277 · App. 10/655,370 · Granted May 29, 2007

Abstract

Claims (104)

1. A method for setting up a direct memory access for a first processor having a local memory, the method comprising the steps of:

determining whether a first DMAC is ready to be set up for handling data transfer for the first processor;

upon a determination that the first DMAC is ready to be set up for handling the data transfer for the first processor, transmitting an access request from a second processor to the first DMAC to set up the first DMAC for data transfer between the local memory and a system memory; and

interrupting the second processor when the first DMAC finishes handling the data transfer;

wherein the step of transmitting the access request from the second processor to the first DMAC to set up the first DMAC for the data transfer comprises the steps of:

transmitting the access request from the second processor to a first bus controller;

transmitting the access request from the first bus controller to a system bus;

transmitting the access request from the system bus to a second bus controller; and

transmitting the access request from the second bus controller to the first DMAC.

2. The method of claim 1 , wherein the step of transmitting the access request from the second processor to a first bus controller comprises the steps of:

transmitting the access request from the second processor to a non-cacheable unit; and

transmitting the access request from the non-cacheable unit to the first bus controller.

3. The method of claim 2 , wherein the non-cacheable unit is a memory map input output (MMIO) access controller.

4. The method of claim 1 , wherein the first processor is configured to poll the first DMAC and to interrupt the second processor when the first DMAC completes the data transfer.

5. The method of claim 1 , further comprising a second DMAC in communication with the local memory, the system memory, and the first processor, wherein the first processor is configured to set up the second DMAC to handle at least a portion of the data transfer between the local memory and the system memory.

6. The method of claim 1 , wherein the first DMAC is also in communication with the first processor, and wherein the first processor is configured to set up the first DMAC to handle the data transfer between the local memory and the system memory.

7. The method of claim 1 , wherein the first DMAC is a proxy DMAC.

8. A method for setting up a direct memory access for a first processor having a local memory, the method comprising the steps of:

determining whether a first DMAC is ready to be set up for handling data transfer for the first processor;

upon a determination that the first DMAC is ready to be set up for handling the data transfer for the first processor, transmitting an access request from a second processor to the first DMAC to set up the first DMAC for data transfer between the local memory and a system memory; and

interrupting the second processor when the first DMAC finishes handling the data transfer;

wherein the step of determining whether the first DMAC is ready to be set up for handling data transfer for the first processor comprises the steps of:

loading a load signal from the first DMAC to the second processor;

analyzing the load signal; and

determining whether the first DMAC is ready to be set up for handling data transfer for the first processor;

wherein the step of loading a load signal from the first DMAC to the second processor comprises the steps of:

transmitting the load signal from the first DMAC to a first bus controller;

transmitting the load signal from the first bus controller to a system bus;

transmitting the load signal from the system bus to a second bus controller;

transmitting the load signal from the second bus controller to the second processor; and

loading the load signal to the second processor;

wherein the step of transmitting the load signal from the second bus controller to the second processor comprises the steps of:

transmitting the load signal from the second bus controller to a non-cacheable unit; and

transmitting the load signal from the non-cacheable unit to the second processor; and wherein the non-cacheable unit is a memory map input output (MMIO) access controller.

9. A system for setting up a direct memory access for a first processor having a local memory, the system comprising:

means for determining whether a first DMAC is ready to be set up for handling data transfer for the first processor;

means for, upon a determination that the first DMAC is ready to be set up for handling the data transfer for the first processor, transmitting an access request from a second processor to the first DMAC to set up the first DMAC for data transfer between the local memory and a system memory; and

means for interrupting the second processor when the first DMAC finishes handling the data transfer;

wherein the means for transmitting the access request from the second processor to the first DMAC to set up the first DMAC for the data transfer comprises:

means for transmitting the access request from the second processor to a first bus controller;

means for transmitting the access request from the second bus controller to a system bus;

means for transmitting the access request from the system bus to a first bus controller; and

means for transmitting the access request from the first bus controller to the first DMAC.

10. The system of claim 9 , wherein the means for transmitting the access request from the second processor to the second bus controller comprises:

means for transmitting the access request from the second processor to a non-cacheable unit; and

means for transmitting the access request from the non-cacheable unit to the second bus controller.

11. The system of claim 10 , wherein the non-cacheable unit is a memory map input output (MMIO) access controller.

12. The system of claim 9 , wherein the first processor is configured to poll the first DMAC and to interrupt the second processor when the first DMAC completes the data transfer.

13. The system of claim 9 , further comprising a second DMAC in communication with the local memory, the system memory, and the first processor, wherein the first processor is configured to set up the second DMAC to handle at least a portion of the data transfer between the local memory and the system memory.

14. The system of claim 9 , wherein the first DMAC is also in communication with the first processor, and wherein the first processor is configured to set up the first DMAC to handle the data transfer between the local memory and the system memory.

15. The system of claim 9 , wherein the first DMAC is a proxy DMAC.

16. A system for setting up a direct memory access for a first processor having a local memory, the system comprising:

means for determining whether a first DMAC is ready to be set up for handling data transfer for the first processor;

means for, upon a determination that the first DMAC is ready to be set up for handling the data transfer for the first processor, transmitting an access request from a second processor to the first DMAC to set up the first DMAC for data transfer between the local memory and a system memory; and

means for interrupting the second processor when the first DMAC finishes handling the data transfer;

wherein the means for determining whether the first DMAC is ready to be set up for handling data transfer for the first processor comprises:

means for loading a load signal from the first DMAC to the second processor;

means for analyzing the load signal; and

means for determining whether the first DMAC is ready to be set up for handling data transfer for the first processor;

wherein the means for loading a load signal from the first DMAC to the second processor comprises:

means for transmitting the load signal from the first DMAC to a first bus controller;

means for transmitting the load signal from the first bus controller to a system bus;

means for transmitting the load signal from the system bus to a second bus controller;

means for transmitting the load signal from the second bus controller to the second processor; and

means for loading the load signal to the second processor;

wherein the means for transmitting the load signal from the second bus controller to the second processor comprises:

means for transmitting the load signal from the second bus controller to a non-cacheable unit; and

means for transmitting the load signal from the non-cacheable unit to the second processor; and

wherein the non-cacheable unit is a memory map input output (MMIO) access controller.

17. A computer program product for setting up a direct memory access for a first processor, the computer program product having a computer-readable medium with a computer program embodied thereon, the computer program comprising:

computer program code for determining whether a first DMAC is ready to be set up for handling data transfer for the first processor;

computer program code for, upon a determination that the first DMAC is ready to be set up for handling the data transfer for the first processor, transmitting an access request from a second processor to the first DMAC to set up the first DMAC for data transfer between the local memory and a system memory; and

computer program code for interrupting the second processor when the first DMAC finishes handling the data transfer;

wherein the computer program code for transmitting the access request from the second processor to the first DMAC to set up the first DMAC for the data transfer comprises:

computer program code for transmitting the access request from the second processor to a second bus controller;

computer program code for transmitting the access request from the second bus controller to a system bus;

computer program code for transmitting the access request from the system bus to a first bus controller; and

computer program code for transmitting the access request from the first bus controller to the first DMAC.

18. The computer program product of claim 17 , wherein the computer program code for transmitting the access request from the second processor to a second bus controller comprises:

computer program code for transmitting the access request from the second processor to a non-cacheable unit; and

computer program code for transmitting the access request from the non-cacheable unit to the second bus controller.

19. The computer program product of claim 18 , wherein the non-cacheable unit is a memory map input output (MMIO) access controller.

20. The computer program product of claim 17 , further comprising computer program code for polling the first DMAC and interrupting the second processor when the first DMAC completes the data transfer.

21. The computer program product of claim 17 , further comprising a second DMAC in communication with the local memory, the system memory, and the first processor, the first processor further comprising computer program code to set up the second DMAC to handle at least a portion of the data transfer between the local memory and the system memory.

22. The computer program product of claim 17 , wherein the first DMAC is also in communication with the first processor, the first processor further comprising computer program code to set up the first DMAC to handle the data transfer between the local memory and the system memory.

23. The computer program product of claim 17 , wherein the first DMAC is a proxy DMAC.

24. A computer program product for setting up a direct memory access for a first processor, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:

computer program code for determining whether a first DMAC is ready to be set up for handling data transfer for the first processor;

computer program code for, upon a determination that the first DMAC is ready to be set up for handling the data transfer for the first processor, transmitting an access request from a second processor to the first DMAC to set up the first DMAC for data transfer between the local memory and a system memory; and

computer program code for interrupting the second processor when the first DMAC finishes handling the data transfer;

wherein the computer program code for determining whether the first DMAC is ready to be set up for handling data transfer for the first processor comprises:

computer program code for loading a load signal from the first DMAC to the second processor;

computer program code for analyzing the load signal; and

computer program code for determining whether the first DMAC is ready to be set up for handling data transfer for the first processor;

wherein the computer program code for loading a load signal from the first DMAC to the second processor comprises:

computer program code for transmitting the load signal from the first DMAC to a first bus controller;

computer program code for transmitting the load signal from the first bus controller to a system bus;

computer program code for transmitting the load signal from the system bus to a second bus controller;

computer program code for transmitting the load signal from the second bus controller to the second processor; and

computer program code for loading the load signal to the second processor;

wherein the computer program code for transmitting the load signal from the second bus controller to the second processor comprises:

computer program code for transmitting the load signal from the second bus controller to a non-cacheable unit; and

computer program code for transmitting the load signal from the non-cacheable unit to the second processor; and

wherein the non-cacheable unit is a memory map input output (MMIO) access controller.

Assignments (8)