IP Library Granted Patent US 6,911,715
Granted Patent B2
US 6,911,715 · App. 10/655,820 · Granted Jun 28, 2005

Bipolar transistors and methods of manufacturing the same

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Quick Facts
Patent No.
US 6,911,715
App. No.
10/655,820
Granted
Jun 28, 2005
Kind
B2
Abstract

A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region. Therefore, it is possible to prevent the base region from extending toward the second collector region due to the third collector region when a high current is injected into the bipolar transistor, thereby improving the capability of driving a current of the bipolar transistor and preventing the occurrence of Kirk effect even during the injection of a high current.

Claims (64)

1. A bipolar transistor comprising:

a first collector region of a first conductive type having high impurity concentration;

a second collector region of a first conductive type having high impurity concentration, the second collection region formed on the first collector region;

a base region of a second conductive type being formed in a predetermined portion of the second collector region; and

an emitter region of a first conductive type being formed in the base region;

wherein a third collector region is further formed between the base region and the second collector region, the third collector region having an impurity concentration at an interface with the base region higher than the remainder of the third collector region.

2. The bipolar transistor of claim 1 , wherein the impurity concentration of the third collector region gradually decreases as the third collector region more closely approaches the second collector region.

3. The bipolar transistor of claim 1 , wherein the third collector region has lower impurity concentration than the first collector region.

4. The bipolar transistor of claim 1 , wherein the first collector region has impurity concentration from 10 14 /cm 3 to 10 20 /cm 3 .

5. The bipolar transistor of claim 1 , wherein the second collector region has impurity concentration from 10 13 /cm 3 to 10 16 /cm 3 .

6. The bipolar transistor of claim 1 , wherein the third collector region has impurity concentration from 10 14 /cm 3 to 10 17 /cm 3 .

7. The bipolar transistor of claim 1 , further comprising:

a base electrode being formed in a predetermined portion of the base region so as to contact the base region;

an emitter electrode being formed in a predetermined portion of the emitter region so as to contact the emitter region; and

a collector electrode being formed at the bottom of the first collector region.

8. The bipolar transistor of claim 1 , wherein the impurity concentrations of the base region, the emitter region, and the first collector region gradually increase toward an interface between the base region and the base electrode, an interface between the emitter region and the emitter electrode, and an interface between the collector region and the collector electrode, respectively.

9. The bipolar transistor of claim 1 , wherein the first conductive type is an n type and the second conductive type is a p type.

10. The bipolar transistor of claim 9 , wherein impurities of the first conductive type are phosphorous ions and impurities of the second conductive type are boron ions.

11. A method of manufacturing a bipolar transistor, comprising:

forming a high-concentration first collector region of a first conductive type at the bottom of a semiconductor substrate that is doped with low-concentration impurities of a first conductive type, thereby defining a second collector region on the semiconductor substrate on the first collector region;

implanting at least one of first conductive impurities for a third collector region and second conductive impurities for a base region into the second collector region;

activating the first conductive impurities for the third collector region and the second conductive impurities for the base region, thereby forming the base region and the third collector region below the base region; and

forming an emitter region in the base region;

wherein the third collector region has higher impurity concentration at an interface with the base region than the remainder of the third collector region.

12. The method of claim 11 , wherein the first conductive impurities are ion-implanted into the third collector region, so that the third collector region has lower impurity concentration than the first collector region.

13. The method of claim 11 , wherein the first collector region and the emitter region are obtained by ion-implanting corresponding impurities into the first collector region and the emitter region and activating the implanted impurities, respectively.

14. The method of claim 11 , after forming the emitter region, further comprising:

depositing an insulating layer on the semiconductor substrate on which the base region and the emitter region are formed;

partially etching the insulating layer to expose predetermined portions of the base region and the emitter region;

forming a base electrode and an emitter electrode on the exposed portions of the based region and the emitter region; and

forming a collector electrode at the first collector region.

15. The method of claim 11 , wherein the first conductive type is an n type and the second conductive type is a p type.

16. The method of claim 11 , wherein the first conductive impurities are phosphorous ions and the second conductive impurities are boron ions.

17. A bipolar transistor, comprising:

a first collector region having a first concentration of a first conductive type;

a second collector region having a second concentration of a first conductive type and formed on the first collector region;

a third collector region having a third concentration of a first conductive type and formed on the second collector region;

a base region formed on a portion of the third collector region; and

an emitter region formed on a portion of the base region;

wherein the third concentration is higher at an interface with the base region than the remainder of the third collector region.

18. The bipolar transistor of claim 17 , wherein the third concentration decreases from the base region to the second collector region.

19. The bipolar transistor of claim 17 , wherein the third concentration is lower than the first concentration.

20. The bipolar transistor of claim 17 , further comprising:

a base electrode contacting a portion of the base region;

an emitter electrode contacting a portion of the emitter region; and

a collector electrode contacting a portion of the first collector region.

21. The bipolar transistor of claim 17 , wherein the first conductive type is an n type and the second conductive type is a p type.

22. A collector for a bipolar transistor, comprising:

a first collector region having a first impurity concentration of a first conductive type;

a second collector region having a second impurity concentration of a first conductive type and formed on the first collector region; and

a third collector region having a third impurity concentration of a first conductive type and formed on the second collector region, wherein the third impurity concentration is highest at a portion of the third collector region furthest from the second collector region.

23. The bipolar transistor of claim 22 , wherein the third concentration decreases from the said furthest portion to the second collector region.

24. A method for making a bipolar transistor, the method comprising:

providing a first collector region having a first concentration of a first conductive type;

providing a second collector region having a second concentration of a first conductive type and formed on the first collector region;

providing a third collector region having a third concentration of a first conductive type and formed on the second collector region;

providing a base region formed on a portion of the third collector region; and

providing an emitter region formed on a portion of the base region;

wherein the third concentration is higher at an interface with the base region than the remainder of the third collector region.

25. The method of claim 24 , wherein the third concentration decreases from the base region to the second collector region.

26. A method for making a collector of bipolar transistor, the method comprising:

providing a first collector region having a first concentration of a first conductive type;

providing a second collector region having a second concentration of a first conductive type and formed on the first collector region; and

providing a third collector region having a third concentration of a first conductive type and formed on the second collector region, wherein the third concentration is highest at the portion of the third collector region furthest from the second collector region.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2005
From: PARK, CHAN-HO; KIM, JIN-MYUNG; PARK, KYEONG-SEOK; HYUN, DONG-HO
To: FAIRCHILD KOREA SEMICONDUCTOR LTD
Reel/Frame 016585/0962 →