Liquid crystal display and thin film transistor array panel therefor
View Patent ↗A thin film transistor array panel is provided, which includes: a gate line and a data line formed on an insulating substrate and intersecting each other; a plurality of common electrodes separated from the gate line and the data line and making an angle of about 7–23 degrees with the gate line; a plurality of pixel electrodes separated from the gate line, the data line, and the common electrodes, extending parallel to the common electrodes, and alternately arranged with the common electrodes; and a thin film transistor connected to the gate line, the data line, and the pixel electrodes, wherein the distance between the common electrode and the pixel electrode is greater than the respective width of the common electrode and the pixel electrode.
1. A thin film transistor array panel comprising:
a gate line and a data line formed on an insulating substrate and intersecting each other;
a plurality of common electrodes separated from the gate line and the data line and making an angle of about 7–23 degrees with the gate line;
a plurality of pixel electrodes separated from the gate line, the data line, and the common electrodes, extending parallel to the common electrodes, and alternately arranged with the common electrodes; and
a thin film transistor connected to the gate line, the data line, and the pixel electrodes,
wherein the distance between a one of the plurality of common electrodes and an adjacent one of the plurality of pixel electrodes is greater than the respective width of the one of the plurality of common electrodes and the adjacent one of the plurality of pixel electrodes.
2. The thin film transistor array panel of claim 1 , wherein the common electrodes include first and second electrodes making an angle of about 15–45 degrees with each other.
3. The thin film transistor array panel of claim 1 , further comprising a connecting electrode connecting the common electrodes and a common electrode line extending parallel to the gate line and connected to the connecting electrode.
4. The thin film transistor array panel of claim 1 , further comprising a pixel electrode line connecting the pixel electrodes and extending parallel to the data lines.
5. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate;
a common electrode line including a plurality of branched common electrodes making an angle of about 7–23 degrees with the gate line;
a gate insulating layer on the gate line;
a semiconductor layer on the gate insulating layer;
a data line formed at least in part on the semiconductor layer;
a pixel electrode line formed at least in part on the semiconductor layer and including a plurality of branched pixel electrodes alternately arranged with the common electrodes; and
a passivation layer formed on the data line and the pixel electrode line,
wherein the distance between the one of the plurality of branched common electrodes and an adjacent one of the plurality of branched pixel electrodes is greater than the respective width of the one of the plurality of branched common electrodes and the adjacent one of the plurality of pixel electrodes.
6. The thin film transistor array panel of claim 5 , wherein the common electrodes comprise first and second electrodes making an angle of about 15–45 degrees with each other.
7. The thin film transistor array panel of claim 6 , wherein the pixel electrodes comprise third and fourth electrodes extending parallel to the first and the second electrodes, respectively.
8. The thin film transistor array panel of claim 5 , further comprising a redundant data line formed on the passivation layer and extending along the data line, the passivation layer having a contact hole for connection between the data line and the redundant data line.
9. The thin film transistor array panel of claim 5 , further comprising a contact assistant formed on the passivation layer, the passivation layer having a contact hole exposing a portion of the data line and covered by the contact assistant.
10. The thin film transistor array panel of claim 5 , wherein the common electrode line extends substantially parallel to the gate line and further includes a frame connecting the common electrodes.
11. The thin film transistor array panel of claim 5 , wherein the pixel electrode line extends substantially parallel to the data line.
12. The thin film transistor array panel of claim 5 , further comprising an ohmic contact disposed between the semiconductor layer and the data line and the pixel electrode line.
13. The thin film transistor array panel of claim 12 , wherein the semiconductor layer has substantially the same planar shape as the data line and the pixel electrode line and the ohmic contact.
14. A liquid crystal display comprising:
a first substrate;
a gate line and a data line formed on the first substrate and intersecting each other;
a plurality of common electrodes separated from the gate line and the data line and making an angle of about 7–23 degrees with the gate line;
a plurality of pixel electrodes separated from the gate line, the data line, and the common electrodes, extending parallel to the common electrodes, and alternately arranged with the common electrodes;
a thin film transistor connected to the gate line, the data line, and the pixel electrodes;
a second substrate; and
a liquid crystal layer interposed between the first substrate and the second substrate,
wherein the distance between a one of the plurality of common electrodes and an adjacent one of the plurality of pixel electrodes is greater than the respective width of the one of the plurality of common electrodes and the adjacent one of the plurality of pixel electrodes.
15. The thin film transistor array panel of claim 1 , further comprising a redundant data line formed on the passivation layer and extending along the data line, the passivation layer having a contact hole for connection between the data line and the redundant data line,
wherein the redundant data line is made of a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), and chromium (Cr).
16. The thin film transistor array panel of claim 8 , wherein the redundant data line is made of a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), and chromium (Cr).
17. The thin film transistor array panel of claim 14 , further comprising:
a redundant data line formed on a passivation layer and extending along the data line, the passivation layer having a contact hole for connection between the data line and the redundant data line, the redundant data line and the data line being connected through the contact hole,
wherein the redundant data line is made of a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), and chromium (Cr).