Printer controller circuit
View Patent ↗An integrated circuit fabricated on a single substrate that includes a data bus and purpose-specific functional units connected to the data bus. The functional units include a halftoner and a printhead interface. A general-purpose processor is connected to the data bus for controlling the functional units, and for coordinating the functional units to print pages. The halftoner may halftone contone color data to a bi-level color layer, and then composit a bi-level black layer over the bi-level color layer.
1. An integrated circuit fabricated on a single substrate comprising:
a data bus;
purpose-specific functional units operatively connected to said data bus, said functional units comprising:
a halftoner; and
a printhead interface; and
a general-purpose processor operatively connected to said data bus for controlling said functional units, wherein said processor is operative to run software that coordinates said functional units to print pages.
2. An integrated circuit according to claim 1 , wherein said processor is operative to print pages in streaming mode.
3. An integrated circuit according to claim 1 , wherein said processor is operative to print pages in single-page mode when the size of said received pages exceeds a memory threshold.
4. An integrated circuit according to claim 3 , wherein said memory threshold is 3 MB.
5. An integrated circuit according to claim 1 , wherein said halftoner is operative to halftone contone color data to a bi-level color layer, and then to composit a bi-level black layer over said bi-level color layer.
6. An integrated circuit according to claim 1 , wherein said halftoner is operative to halftone contone CMYK data to a bi-level CMYK layer, and then to composit a bi-level black layer over said bi-level CMYK layer.
7. An integrated circuit according to claim 1 , wherein said processor is operative to transfer bi-level color data to said printhead interface at a constant required rate.
8. An integrated circuit according to claim 1 , further comprising a multi-channel DMA controller operatively connected to said data bus, wherein each of said functional units further comprises one or more on-chip input and/or output FIFOs, and wherein each FIFO is allocated a separate channel in said multi-channel DMA controller.
9. An integrated circuit according to claim 8 , wherein said DMA controller is operative to interrupt said processor when a data transfer is complete.
10. An integrated circuit according to claim 1 , wherein said halftoner is operative to consume black and contone data according to specified black and contone page widths and output scaled data to said printhead interface.
11. An integrated circuit according to claim 1 , wherein said printhead interface comprises:
a line loader/format unit; and
a Memjet interface operatively connected to said line loader/format unit; wherein said Memjet interface transfers data to a Memjet printhead.
12. An integrated circuit according to claim 11 , wherein said line loader/format unit is operative to load dots for a given print line into local buffer storage and format said dots into an order required for said Memjet printhead.