Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays
View Patent ↗A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.
1. A method of fabricating a fieldless array, the method comprising:
forming an oxide-nitride-oxide (ONO) layer over a surface of a semiconductor region;
patterning the ONO layer to create a first set of ONO structures that define locations for a plurality of diffusion bit lines of the fieldless array; then
forming a plurality of word lines over the first set of ONO structures; and then
patterning the first set of ONO structures, thereby creating a second set of ONO structures, wherein the second set of ONO structures are located entirely under the plurality of word lines.
2. The method of claim 1 , further comprising forming dielectric sidewall spacers adjacent to the word lines.
3. The method of claim 1 , further comprising forming gap-filling oxide between the word lines.
4. The method of claim 1 , further comprising implanting diffusion bit lines through the first set of ONO structures.
5. The method of claim 4 , further comprising thermally growing bit line oxide regions over the diffusion bit lines.
6. The method of claim 4 , wherein the diffusion bit lines extend along a first axis, and the word lines extend along a second axis, perpendicular to the first axis.
7. The method of claim 1 , wherein the steps of forming a plurality of word lines and patterning the first set of ONO structures comprise:
depositing a layer of polysilicon over the first set of ONO structures;
forming a photoresist mask over the layer of polysilicon;
etching the layer of polysilicon through the photoresist mask; and
etching the first set of ONO structures through the photoresist mask.
8. The method of claim 7 , wherein the steps of etching the layer of polysilicon and the first set of ONO structures are implemented by a reactive ion etch (RIE).
9. The method of claim 7 , wherein the step of etching the first set of ONO structures is implemented by a series of wet etches.
10. The method of claim 7 , wherein the step of etching the first set of ONO structures is implemented by a wet etch and a dry/reactive ion etch (RIE).
11. The method of claim 7 , wherein the step of etching the first set of ONO structures is extended to etch the semiconductor substrate to a depth of 50 to 400 Angstroms.
12. The method of claim 7 , further comprising performing a re-oxidation step after the step of etching the first set of ONO structures.
13. The method of claim 12 , wherein the re-oxidation step results in the formation of about 20–200 Angstroms of silicon oxide.
14. The method of claim 7 , wherein the step of etching the first set of ONO structures results in the removal of portions of the first set of ONO structures under the layer of polysilicon.
15. The method of claim 1 , wherein the steps of forming a plurality of word lines and patterning the first set of ONO structures comprise:
depositing a layer of polysilicon over the first set of ONO structures;
patterning the layer of polysilicon;
depositing a thin dielectric spacer having a thickness up to about 400 Angstroms over the patterned layer of polysilicon;
etching back the thin dielectric spacer layer, prior to etching the first set of ONO structures
etching the first set of ONO structures through the etched back thin dielectric spacer layer.