Interconnect, interconnect forming method, thin film transistor, and display device
View Patent ↗An interconnect forming method according to the present invention includes a step of forming a barrier film for metal diffusion on an insulator film, a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process, a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process, and a step of etching the barrier film for metal diffusion using the metal conductive layer as a mask.
1. An interconnect forming method comprising:
a step of forming a barrier film for metal diffusion on an insulator base;
a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process; and
a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process.
2. An interconnect forming method comprising:
a step of forming a barrier film for metal diffusion on an insulator base;
a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process;
a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process; and
a step of etching the barrier film for metal diffusion using the metal conductive layer as a mask.
3. An interconnect forming method comprising:
a step of forming a barrier film for metal diffusion on an insulator base;
a step of selectively forming a metal seed layer on the barrier film for metal diffusion using an electroless plating process;
a step of etching the barrier film for metal diffusion using the metal seed layer as a mask; and
a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process.
4. The interconnect forming method according to claim 1 , wherein the insulator base has a substrate and an underlying insulator film provided on the substrate.
5. An interconnect forming method comprising:
a step of forming a barrier film for metal diffusion on an insulator base;
a step of selectively forming a metal seed layer on the barrier film for metal diffusion; and
a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process,
further comprising a step of carrying out annealing after the metal seed layer has been formed to reduce film stress that may occur in the metal seed layer.
6. An interconnect forming method comprising:
a step of forming a barrier film for metal diffusion on an insulator base;
a step of selectively forming a metal seed layer on the barrier film for metal diffusion; and
a step of selectively forming a metal conductive layer on the metal seed layer using an electroplating process,
wherein the step of selectively forming the metal seed layer on the barrier film for metal diffusion using the electroless plating process uses a mask composed of a photosensitive resin and having a trench shaped so as to correspond to an area in which the metal seed layer is formed, to execute the electroless plating process to form the metal seed layer on the barrier film for metal diffusion exposed from this trench.
7. The interconnect forming method according to claim 2 , wherein the insulator base has a substrate and an underlying insulator film provided on the substrate.
8. The interconnect forming method according to claim 2 , further comprising a step of carrying out annealing after the metal seed layer has been formed to reduce film stress that may occur in the metal seed layer.
9. The interconnect forming method according to claim 2 , wherein the step of selectively forming the metal seed layer on the barrier film for metal diffusion using the electroless plating process uses a mask composed of a photosensitive resin and having a trench shaped so as to correspond to an area in which the metal seed layer is formed, to execute the electroless plating process to form the metal seed layer on the barrier film for metal diffusion exposed from this trench.
10. The interconnect forming method according to claims 3 , wherein the insulator base has a substrate and an underlying insulator film provided on the substrate.
11. The interconnect forming method according to claim 3 , further comprising a step of carrying out annealing after the metal seed layer has been formed to reduce film stress that may occur in the metal seed layer.
12. The interconnect forming method according to claim 3 , wherein the step of selectively forming the metal seed layer on the barrier film for metal diffusion using the electroless plating process uses a mask composed of a photosensitive resin and having a trench shaped so as to correspond to an area in which the metal seed layer is formed, to execute the electroless plating process to form the metal seed layer on the barrier film for metal diffusion exposed from this trench.