IP Library Granted Patent US 6,922,398
Granted Patent B2
US 6,922,398 · App. 10/662,202 · Granted Jul 26, 2005

Optimized switch card

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Quick Facts
Patent No.
US 6,922,398
App. No.
10/662,202
Granted
Jul 26, 2005
Kind
B2
Abstract

An optimized network ( 300 ), includes providing a switch card topology ( 350 ) having a plurality of switching elements ( 305 ), where the plurality of switching elements are arranged to form a switch configuration ( 303 ). N number of payload interfaces ( 307 ) are coupled to the switch configuration, where each of the N number of payload interfaces is coupled to interface with one of a plurality of payload slots ( 308 ). A set of N payload module configurations ( 402, 502 ) is characterized by a sequential addition ( 320 ) of a payload module ( 304 ) into each of the plurality of payload slots, where the sequential addition of the payload module couples the payload module to the network. N number of payload interfaces are coupled to the switch configuration such that a latency function ( 616 ) is minimized for the switch configuration and the set of N payload module configurations.

Claims (31)

1. A switch card, comprising:

a plurality of switching elements, wherein the plurality of switching elements are arranged to form a switch configuration; and

N number of payload interfaces, wherein each of the n number of payload interfaces is coupled to interface with one of a plurality of payload slots, wherein the N number of payload interfaces are coupled to the switch configuration such that a latency function is minimized for the switch configuration and a set of N payload module configurations, and wherein the set of N payload module configurations is characterized by a sequential addition of a payload module into each of the plurality of payload slots.

2. The switch card of claim 1 , wherein the latency function is a root-mean squared latency function.

3. The switch card of claim 1 , wherein the latency function is an arithmetic mean latency function.

4. The switch card of claim 1 , wherein the latency function is a normalized root-mean squared latency function.

5. The switch card of claim 1 , wherein the latency function is a normalized arithmetic mean latency function.

6. The switch card of claim 1 , wherein the sequential addition comprises a first end to a second end sequential addition.

7. The switch card of claim 1 , wherein the sequential addition comprises a second end to a first end sequential addition.

8. The switch card of claim 1 , wherein the plurality of switching elements comprises M number of switching elements coupled to the N number of payload interfaces, wherein each of the M number of switching elements has a plurality of ports, and wherein the sequential addition comprises populating all of the plurality of ports on one of the M number of switching elements, one of the M number of switching elements at a time.

9. A network, comprising:

a switch card having a plurality of switching elements, wherein the plurality of switching elements are arranged to form a switch configuration;

N number of payload interfaces coupled to the switch configuration, wherein each of the N number of payload interfaces is coupled to interface with one of a plurality of payload slots; and

a set of N payload module configurations, wherein the set of N payload module configurations is characterized by a sequential addition of a payload module into each of the plurality of payload slots, wherein the sequential addition of the payload module couples the payload module to the network, and wherein the N number of payload interfaces are coupled to the switch configuration such that a latency function is minimized for the switch configuration and the set of N payload module configurations.

10. The network of claim 9 , wherein the latency function is a root-mean squared latency function.

11. The network of claim 9 , wherein the latency function is an arithmetic mean latency function.

12. The network of claim 9 , wherein the latency function is a normalized root-mean squared latency function.

13. The network of claim 9 , wherein the latency function is a normalized arithmetic mean latency function.

14. The network of claim 9 , wherein the sequential addition comprises a first end to a second end sequential addition.

15. The network of claim 9 , wherein the sequential addition comprises a second end to a first end sequential addition.

16. The network of claim 9 , wherein the plurality of switching elements comprises M number of switching elements coupled to the N number of payload interfaces, wherein each of the M number of switching elements has a plurality of ports, and wherein the sequential addition comprises populating all of the plurality of ports on one of the M number of switching elements, one of the M number of switching elements at a time.

17. A switch card, comprising:

a plurality of switching elements, wherein the plurality of switching elements are arranged to form a switch configuration; and

N number of payload interfaces, wherein each of the N number of payload interfaces is coupled to interface with one of a plurality of payload slots, wherein the N number of payload interfaces are coupled to the switch configuration so as to minimize an all-to-all transfer time based on minimizing a latency function for the switch configuration and a set of N payload module configurations, and wherein the set of N payload module configurations is characterized by a sequential addition of a payload module into each of the plurality of payload slots.

18. The switch card of claim 17 , wherein the latency function is a root-mean squared latency function.

19. The switch card of claim 17 , wherein the latency function is an arithmetic mean latency function.

20. The switch card of claim 17 , wherein the latency function is a normalized root-mean squared latency function.

21. The switch card of claim 17 , wherein the latency function is a normalized arithmetic mean latency function.

22. The switch card of claim 17 , wherein the sequential addition comprises a first end to a second end sequential addition.

23. The switch card of claim 17 , wherein the sequential addition comprises a second end to a first end sequential addition.

24. The switch card of claim 17 , wherein the plurality of switching elements comprises M number of switching elements coupled to the N number of payload interfaces, wherein each of the M number of switching elements has a plurality of ports, and wherein the sequential addition comprises populating all of the plurality of ports on one of the M number of switching elements, one of the M number of switching elements at a time.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jul 9, 2019
From: ARTESYN EMBEDDED COMPUTING, INC. (F/K/A EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.)
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049698/0222 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Jul 8, 2019
From: BANK OF AMERICA, N.A.
To: ARTESYN EMBEDDED COMPUTING, INC. (F/K/A EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.)
Reel/Frame 049694/0096 →
SECURITY AGREEMENT Recorded Nov 26, 2013
From: ARTESYN TECHNOLOGIES, INC.; ARTESYN NORTH AMERICA LLC; EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 031731/0048 →
SECURITY AGREEMENT Recorded Nov 25, 2013
From: ARTESYN TECHNOLOGIES, INC.; ARTESYN NORTH AMERICA LLC; EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT AND GRANTEE
Reel/Frame 031719/0417 →