Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer
View Patent ↗The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space is designed considering a thickness of a cutting edge of a blade and relative positioning error, and the blade does not cross any metal wirings when the blade passes through the dicing area, thereby preventing the generation of an abruption or a burr due to the dicing to enhance a yield in IC production.
1. A semiconductor wafer comprising:
a plurality of chip areas in which a number of semiconductor elements are formed;
a dicing area provided at the outside of each chip area;
a characteristic evaluating element formed in the dicing area; and
a probe-contactable monitoring pad formed in the dicing area and electrically connected to the characteristic evaluating element;
wherein the monitoring pad includes two or more exposed surfaces divided via a space that is approximately parallel to the longitudinal direction of the dicing area,
the two or more exposed surfaces are electrically connected with each other via a metal wiring of an inner layer;
one of the exposed surfaces is arranged in an area for cut away by a dicing blade,
another of the exposed surfaces is arranged outside of the area for cut away by the dicing blade, and
a space between the one and the another of the exposed surfaces includes an area for positioning a cutting line by dicing blade.
2. The semiconductor wafer according to claim 1 , wherein the monitoring pad is formed of metal wirings of plural layers and said exposed surfaces are configured of metal wirings of the uppermost layer and at least one layer among the metal wirings of the inner layer is divided with the same shape as the exposed surface.